Module Definition
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Module : prim_lc_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_lc_sync 100.00 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync 100.00 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en 100.00 100.00 100.00


Module Instance : tb.dut.u_prim_lc_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.00 100.00 100.00 100.00 95.00 50.00 u_tlul_lc_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 
Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 
Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 
Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 2706 2706 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.OutputDelay_A 2050867978 2050626440 0 5412
gen_no_flops.OutputDelay_A 1025433989 1025327828 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2706 2706 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T7 3 3 0 0
T8 3 3 0 0
T11 3 3 0 0
T12 3 3 0 0
T13 3 3 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 2856 2655 0 0
T2 103746 103539 0 0
T3 116337 99951 0 0
T4 161187 160956 0 0
T5 47154 30750 0 0
T7 211533 211308 0 0
T8 214527 214308 0 0
T11 275208 274923 0 0
T12 104088 103872 0 0
T13 6048 5889 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2050867978 2050626440 0 5412
T1 1904 1764 0 6
T2 69164 69020 0 6
T3 77558 66148 0 6
T4 107458 107298 0 6
T5 31436 20014 0 6
T7 141022 140866 0 6
T8 143018 142866 0 6
T11 183472 183276 0 6
T12 69392 69242 0 6
T13 4032 3920 0 6

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1025433989 1025327828 0 0
T1 952 885 0 0
T2 34582 34513 0 0
T3 38779 33317 0 0
T4 53729 53652 0 0
T5 15718 10250 0 0
T7 70511 70436 0 0
T8 71509 71436 0 0
T11 91736 91641 0 0
T12 34696 34624 0 0
T13 2016 1963 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 
Assert Coverage for Instance : tb.dut.u_prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 902 902 0 0
OutputsKnown_A 1025433989 1025327828 0 0
gen_flops.OutputDelay_A 1025433989 1025313220 0 2706


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 902 902 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1025433989 1025327828 0 0
T1 952 885 0 0
T2 34582 34513 0 0
T3 38779 33317 0 0
T4 53729 53652 0 0
T5 15718 10250 0 0
T7 70511 70436 0 0
T8 71509 71436 0 0
T11 91736 91641 0 0
T12 34696 34624 0 0
T13 2016 1963 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1025433989 1025313220 0 2706
T1 952 882 0 3
T2 34582 34510 0 3
T3 38779 33074 0 3
T4 53729 53649 0 3
T5 15718 10007 0 3
T7 70511 70433 0 3
T8 71509 71433 0 3
T11 91736 91638 0 3
T12 34696 34621 0 3
T13 2016 1960 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 902 902 0 0
OutputsKnown_A 1025433989 1025327828 0 0
gen_no_flops.OutputDelay_A 1025433989 1025327828 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 902 902 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1025433989 1025327828 0 0
T1 952 885 0 0
T2 34582 34513 0 0
T3 38779 33317 0 0
T4 53729 53652 0 0
T5 15718 10250 0 0
T7 70511 70436 0 0
T8 71509 71436 0 0
T11 91736 91641 0 0
T12 34696 34624 0 0
T13 2016 1963 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1025433989 1025327828 0 0
T1 952 885 0 0
T2 34582 34513 0 0
T3 38779 33317 0 0
T4 53729 53652 0 0
T5 15718 10250 0 0
T7 70511 70436 0 0
T8 71509 71436 0 0
T11 91736 91641 0 0
T12 34696 34624 0 0
T13 2016 1963 0 0

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 
Assert Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 902 902 0 0
OutputsKnown_A 1025433989 1025327828 0 0
gen_flops.OutputDelay_A 1025433989 1025313220 0 2706


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 902 902 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1025433989 1025327828 0 0
T1 952 885 0 0
T2 34582 34513 0 0
T3 38779 33317 0 0
T4 53729 53652 0 0
T5 15718 10250 0 0
T7 70511 70436 0 0
T8 71509 71436 0 0
T11 91736 91641 0 0
T12 34696 34624 0 0
T13 2016 1963 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1025433989 1025313220 0 2706
T1 952 882 0 3
T2 34582 34510 0 3
T3 38779 33074 0 3
T4 53729 53649 0 3
T5 15718 10007 0 3
T7 70511 70433 0 3
T8 71509 71433 0 3
T11 91736 91638 0 3
T12 34696 34621 0 3
T13 2016 1960 0 3

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