Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1037806900	247164	0	0
ctrl_regwen_rd_A	1037806900	4090	0	0
exec_rd_A	1037806900	3846	0	0
exec_regwen_rd_A	1037806900	4016	0	0
readback_rd_A	1037806900	2920	0	0
readback_regwen_rd_A	1037806900	2612	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037806900	247164	0	0
T6	304227	0	0	0
T14	1541	0	0	0
T15	11568	0	0	0
T21	25646	1961	0	0
T23	0	2708	0	0
T24	0	8364	0	0
T25	0	4389	0	0
T26	0	3067	0	0
T27	74307	0	0	0
T29	71234	0	0	0
T30	72817	0	0	0
T31	33830	0	0	0
T34	70380	0	0	0
T35	57936	0	0	0
T37	0	4698	0	0
T38	0	3712	0	0
T52	0	5568	0	0
T77	0	2005	0	0
T78	0	5956	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037806900	4090	0	0
T10	809169	0	0	0
T37	150992	216	0	0
T39	337997	0	0	0
T44	269519	0	0	0
T49	0	241	0	0
T50	0	248	0	0
T53	72644	0	0	0
T54	78525	0	0	0
T55	465250	0	0	0
T56	34590	0	0	0
T57	85605	0	0	0
T58	1656	0	0	0
T129	0	115	0	0
T130	0	138	0	0
T131	0	301	0	0
T132	0	403	0	0
T133	0	352	0	0
T134	0	96	0	0
T135	0	208	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037806900	3846	0	0
T10	809169	0	0	0
T37	150992	163	0	0
T39	337997	0	0	0
T44	269519	0	0	0
T49	0	302	0	0
T50	0	282	0	0
T53	72644	0	0	0
T54	78525	0	0	0
T55	465250	0	0	0
T56	34590	0	0	0
T57	85605	0	0	0
T58	1656	0	0	0
T129	0	72	0	0
T130	0	124	0	0
T131	0	239	0	0
T132	0	423	0	0
T133	0	288	0	0
T134	0	83	0	0
T135	0	212	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037806900	4016	0	0
T10	809169	0	0	0
T37	150992	165	0	0
T39	337997	0	0	0
T44	269519	0	0	0
T49	0	253	0	0
T50	0	263	0	0
T53	72644	0	0	0
T54	78525	0	0	0
T55	465250	0	0	0
T56	34590	0	0	0
T57	85605	0	0	0
T58	1656	0	0	0
T129	0	48	0	0
T130	0	114	0	0
T131	0	257	0	0
T132	0	333	0	0
T133	0	313	0	0
T134	0	63	0	0
T135	0	227	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037806900	2920	0	0
T10	809169	0	0	0
T37	150992	198	0	0
T39	337997	0	0	0
T44	269519	0	0	0
T49	0	271	0	0
T50	0	220	0	0
T53	72644	0	0	0
T54	78525	0	0	0
T55	465250	0	0	0
T56	34590	0	0	0
T57	85605	0	0	0
T58	1656	0	0	0
T129	0	98	0	0
T130	0	56	0	0
T131	0	200	0	0
T132	0	287	0	0
T133	0	319	0	0
T134	0	103	0	0
T135	0	282	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037806900	2612	0	0
T10	809169	0	0	0
T37	150992	180	0	0
T39	337997	0	0	0
T44	269519	0	0	0
T49	0	189	0	0
T50	0	218	0	0
T53	72644	0	0	0
T54	78525	0	0	0
T55	465250	0	0	0
T56	34590	0	0	0
T57	85605	0	0	0
T58	1656	0	0	0
T129	0	119	0	0
T130	0	91	0	0
T131	0	248	0	0
T132	0	271	0	0
T133	0	265	0	0
T134	0	120	0	0
T135	0	239	0	0