Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

17208656

1

T1

78

T4

47

T8

3082

full_word

155873657

1

T1

910

T4

464

T5

684

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	173082003	1			T1	988		T4	511		T5	684
auto[TlIntgErrCmd]	105	1			T62	9		T63	7		T64	5
auto[TlIntgErrData]	100	1			T62	5		T63	4		T64	7
auto[TlIntgErrBoth]	105	1			T62	6		T63	9		T64	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83451377

1

T1

487

T4

261

T5

348

auto[1]

89630936

1

T1

501

T4

250

T5

336

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8425463	1			T1	40		T4	32		T8	1576
auto[TlIntgErrNone]	partial	auto[1]	8782910	1			T1	38		T4	15		T8	1506
auto[TlIntgErrNone]	full_word	auto[0]	75025763	1			T1	447		T4	229		T5	348
auto[TlIntgErrNone]	full_word	auto[1]	80847867	1			T1	463		T4	235		T5	336
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T62	3		T63	4		T64	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T62	4		T63	3		T64	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T127	1		T128	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T62	2		T130	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T62	3		T63	1		T64	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T63	1		T64	4		T120	4
auto[TlIntgErrData]	full_word	auto[0]	9	1			T62	1		T63	2		T120	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T62	1		T120	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T62	3		T63	3		T64	6
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T62	3		T63	6		T64	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T125	1		T127	2		T131	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T129	1		-	-		-	-