Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	951631	1			T31	107		T10	22		T34	255
auto[1]	11241312	1			T5	348		T8	17		T13	1929
auto[2]	740001	1			T31	69		T10	22		T34	191
auto[3]	10969197	1			T5	335		T8	10		T13	1873

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15163747	1			T5	683		T8	1		T13	2568
auto[1]	2216378	1			T8	4		T13	542		T6	12
auto[2]	2267034	1			T8	4		T13	550		T6	17
auto[3]	4254982	1			T8	18		T13	142		T6	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9785599

1

T5

683

T8

27

T13

3802

auto[1]

14116542

1

T32

1

T35

1

T36

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	409756	1			T31	2		T10	22		T34	8
auto[0]	auto[0]	auto[1]	42214	1			T31	13		T34	35		T26	154
auto[0]	auto[0]	auto[2]	42230	1			T31	14		T34	29		T26	173
auto[0]	auto[0]	auto[3]	75288	1			T31	78		T34	183		T26	26
auto[0]	auto[1]	auto[0]	3418728	1			T5	348		T8	1		T13	1299
auto[0]	auto[1]	auto[1]	356575	1			T8	2		T13	277		T6	2
auto[0]	auto[1]	auto[2]	369489	1			T8	2		T13	285		T6	8
auto[0]	auto[1]	auto[3]	356944	1			T8	12		T13	68		T31	239
auto[0]	auto[2]	auto[0]	300878	1			T10	21		T26	969		T145	129
auto[0]	auto[2]	auto[1]	35522	1			T26	95		T145	25		T22	3
auto[0]	auto[2]	auto[2]	33324	1			T31	15		T10	1		T34	38
auto[0]	auto[2]	auto[3]	53653	1			T31	54		T34	153		T26	5
auto[0]	auto[3]	auto[0]	3258700	1			T5	335		T13	1269		T14	2335
auto[0]	auto[3]	auto[1]	349274	1			T8	2		T13	265		T6	10
auto[0]	auto[3]	auto[2]	364064	1			T8	2		T13	265		T6	9
auto[0]	auto[3]	auto[3]	318960	1			T8	6		T13	74		T6	1
auto[1]	auto[0]	auto[0]	12641	1			T26	1		T109	414		T110	436
auto[1]	auto[0]	auto[1]	56889	1			T109	2016		T110	2051		T144	640
auto[1]	auto[0]	auto[2]	56791	1			T109	2073		T110	1967		T144	669
auto[1]	auto[0]	auto[3]	255822	1			T109	9166		T110	8880		T144	3020
auto[1]	auto[1]	auto[0]	3877921	1			T54	51182		T105	47877		T106	79239
auto[1]	auto[1]	auto[1]	688712	1			T54	5148		T105	4892		T106	7807
auto[1]	auto[1]	auto[2]	669610	1			T54	5011		T105	4848		T106	7947
auto[1]	auto[1]	auto[3]	1503333	1			T35	1		T54	509		T105	456
auto[1]	auto[2]	auto[0]	8214	1			T109	241		T110	271		T146	357
auto[1]	auto[2]	auto[1]	37749	1			T109	1203		T110	1146		T146	1558
auto[1]	auto[2]	auto[2]	49333	1			T109	2231		T110	2194		T144	588
auto[1]	auto[2]	auto[3]	221328	1			T109	10032		T110	9701		T144	2622
auto[1]	auto[3]	auto[0]	3876909	1			T36	1		T52	1		T54	51355
auto[1]	auto[3]	auto[1]	649443	1			T32	1		T54	5171		T105	4907
auto[1]	auto[3]	auto[2]	682193	1			T54	5188		T105	4823		T106	7895
auto[1]	auto[3]	auto[3]	1469654	1			T54	509		T105	549		T106	775