Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1180451536	247423	0	0
ctrl_regwen_rd_A	1180451536	5854	0	0
exec_rd_A	1180451536	5995	0	0
exec_regwen_rd_A	1180451536	6229	0	0
readback_rd_A	1180451536	3803	0	0
readback_regwen_rd_A	1180451536	3577	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180451536	247423	0	0
T6	193804	0	0	0
T7	23934	0	0	0
T11	31390	1234	0	0
T12	95556	0	0	0
T13	71675	0	0	0
T14	71705	0	0	0
T15	891	0	0	0
T24	0	13893	0	0
T25	0	1793	0	0
T27	33697	0	0	0
T31	92699	0	0	0
T32	78267	0	0	0
T45	0	2169	0	0
T67	0	1985	0	0
T68	0	591	0	0
T69	0	4626	0	0
T70	0	1733	0	0
T71	0	3280	0	0
T72	0	5333	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180451536	5854	0	0
T6	193804	0	0	0
T7	23934	0	0	0
T11	31390	53	0	0
T12	95556	0	0	0
T13	71675	0	0	0
T14	71705	0	0	0
T15	891	0	0	0
T27	33697	0	0	0
T31	92699	0	0	0
T32	78267	0	0	0
T45	0	170	0	0
T46	0	579	0	0
T67	0	135	0	0
T68	0	59	0	0
T71	0	238	0	0
T115	0	81	0	0
T116	0	214	0	0
T117	0	214	0	0
T118	0	264	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180451536	5995	0	0
T6	193804	0	0	0
T7	23934	0	0	0
T11	31390	31	0	0
T12	95556	0	0	0
T13	71675	0	0	0
T14	71705	0	0	0
T15	891	0	0	0
T27	33697	0	0	0
T31	92699	0	0	0
T32	78267	0	0	0
T45	0	180	0	0
T46	0	585	0	0
T67	0	87	0	0
T68	0	66	0	0
T71	0	279	0	0
T115	0	143	0	0
T116	0	216	0	0
T117	0	284	0	0
T118	0	323	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180451536	6229	0	0
T6	193804	0	0	0
T7	23934	0	0	0
T11	31390	33	0	0
T12	95556	0	0	0
T13	71675	0	0	0
T14	71705	0	0	0
T15	891	0	0	0
T27	33697	0	0	0
T31	92699	0	0	0
T32	78267	0	0	0
T45	0	121	0	0
T46	0	546	0	0
T67	0	108	0	0
T68	0	76	0	0
T71	0	357	0	0
T115	0	158	0	0
T116	0	209	0	0
T117	0	223	0	0
T118	0	317	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180451536	3803	0	0
T6	193804	0	0	0
T7	23934	0	0	0
T11	31390	52	0	0
T12	95556	0	0	0
T13	71675	0	0	0
T14	71705	0	0	0
T15	891	0	0	0
T27	33697	0	0	0
T31	92699	0	0	0
T32	78267	0	0	0
T45	0	221	0	0
T46	0	564	0	0
T67	0	83	0	0
T68	0	24	0	0
T71	0	271	0	0
T115	0	123	0	0
T116	0	141	0	0
T117	0	282	0	0
T118	0	303	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1180451536	3577	0	0
T6	193804	0	0	0
T7	23934	0	0	0
T11	31390	37	0	0
T12	95556	0	0	0
T13	71675	0	0	0
T14	71705	0	0	0
T15	891	0	0	0
T27	33697	0	0	0
T31	92699	0	0	0
T32	78267	0	0	0
T45	0	99	0	0
T46	0	525	0	0
T67	0	79	0	0
T68	0	31	0	0
T71	0	341	0	0
T115	0	155	0	0
T116	0	190	0	0
T117	0	122	0	0
T118	0	221	0	0