Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16143223

1

T2

34

T4

91

T5

1268

full_word

156758866

1

T2

454

T4

976

T5

296

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	172901799	1			T2	488		T4	1067		T5	1564
auto[TlIntgErrCmd]	97	1			T67	3		T68	10		T69	9
auto[TlIntgErrData]	104	1			T67	5		T68	6		T69	5
auto[TlIntgErrBoth]	89	1			T67	2		T68	4		T69	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83570129

1

T2

257

T4

560

T5

796

auto[1]

89331960

1

T2

231

T4

507

T5

768

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7904799	1			T2	19		T4	55		T5	648
auto[TlIntgErrNone]	partial	auto[1]	8238154	1			T2	15		T4	36		T5	620
auto[TlIntgErrNone]	full_word	auto[0]	75665209	1			T2	238		T4	505		T5	148
auto[TlIntgErrNone]	full_word	auto[1]	81093637	1			T2	216		T4	471		T5	148
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T67	1		T68	4		T69	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T67	2		T68	6		T69	7
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T124	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T125	1		T126	1		T127	2
auto[TlIntgErrData]	partial	auto[0]	48	1			T68	4		T69	1		T128	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T67	5		T68	2		T69	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T69	1		T129	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T69	2		T126	1		T130	2
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T67	1		T68	2		T69	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T67	1		T68	2		T69	5
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T131	1		T132	1		T127	1