Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	719999	1			T35	3		T32	819		T23	2153
auto[1]	10899609	1			T5	1		T7	465		T11	622
auto[2]	552133	1			T5	1		T35	2		T32	750
auto[3]	10610628	1			T5	2		T7	526		T11	592

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14515038	1			T7	991		T11	820		T21	1916
auto[1]	2135004	1			T11	177		T32	200		T36	1107
auto[2]	2169713	1			T5	1		T11	182		T35	1
auto[3]	3962614	1			T5	3		T11	35		T35	9

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9773746

1

T5

4

T7

991

T11

1214

auto[1]

13008623

1

T23

2

T54

54271

T58

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	227122	1			T32	665		T9	17		T143	709
auto[0]	auto[0]	auto[1]	24034	1			T32	72		T23	17		T143	76
auto[0]	auto[0]	auto[2]	23870	1			T32	75		T23	13		T9	1
auto[0]	auto[0]	auto[3]	57175	1			T35	3		T32	7		T23	2121
auto[0]	auto[1]	auto[0]	3700614	1			T7	465		T11	429		T21	989
auto[0]	auto[1]	auto[1]	376814	1			T11	86		T32	70		T36	573
auto[0]	auto[1]	auto[2]	387159	1			T11	91		T32	8		T36	532
auto[0]	auto[1]	auto[3]	242895	1			T5	1		T11	16		T35	3
auto[0]	auto[2]	auto[0]	157560	1			T32	640		T9	29		T10	1
auto[0]	auto[2]	auto[1]	19386	1			T32	54		T23	111		T9	2
auto[0]	auto[2]	auto[2]	22322	1			T32	52		T23	15		T9	2
auto[0]	auto[2]	auto[3]	43004	1			T5	1		T35	2		T32	4
auto[0]	auto[3]	auto[0]	3525687	1			T7	526		T11	391		T21	927
auto[0]	auto[3]	auto[1]	366948	1			T11	91		T32	4		T36	534
auto[0]	auto[3]	auto[2]	378545	1			T5	1		T11	91		T35	1
auto[0]	auto[3]	auto[3]	220611	1			T5	1		T11	19		T35	1
auto[1]	auto[0]	auto[0]	12788	1			T111	93		T142	927		T144	943
auto[1]	auto[0]	auto[1]	57398	1			T111	376		T142	4112		T144	4145
auto[1]	auto[0]	auto[2]	57899	1			T111	363		T142	4155		T144	4228
auto[1]	auto[0]	auto[3]	259713	1			T23	2		T111	1700		T142	18731
auto[1]	auto[1]	auto[0]	3445052	1			T54	22751		T58	1		T66	43412
auto[1]	auto[1]	auto[1]	644377	1			T54	1982		T66	4556		T110	5560
auto[1]	auto[1]	auto[2]	618532	1			T54	2136		T66	4279		T145	1
auto[1]	auto[1]	auto[3]	1484166	1			T54	237		T66	468		T110	587
auto[1]	auto[2]	auto[0]	9084	1			T142	866		T144	863		T146	796
auto[1]	auto[2]	auto[1]	40922	1			T142	3798		T144	3945		T146	3505
auto[1]	auto[2]	auto[2]	47047	1			T111	314		T142	2820		T144	3501
auto[1]	auto[2]	auto[3]	212808	1			T111	1516		T142	12738		T144	15964
auto[1]	auto[3]	auto[0]	3437131	1			T54	22730		T58	1		T66	43149
auto[1]	auto[3]	auto[1]	605125	1			T54	2243		T66	4262		T110	6420
auto[1]	auto[3]	auto[2]	634339	1			T54	1998		T59	2		T66	4276
auto[1]	auto[3]	auto[3]	1442242	1			T54	194		T66	433		T110	559