Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1132171066	231298	0	0
ctrl_regwen_rd_A	1132171066	6497	0	0
exec_rd_A	1132171066	5920	0	0
exec_regwen_rd_A	1132171066	6633	0	0
readback_rd_A	1132171066	4536	0	0
readback_regwen_rd_A	1132171066	3914	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132171066	231298	0	0
T9	101465	0	0	0
T22	89168	4023	0	0
T23	244463	0	0	0
T25	196997	10232	0	0
T26	0	1275	0	0
T54	176206	0	0	0
T55	68092	0	0	0
T56	42264	0	0	0
T57	33538	0	0	0
T61	0	10081	0	0
T63	0	8129	0	0
T64	48269	0	0	0
T65	76522	0	0	0
T74	0	1206	0	0
T75	0	3024	0	0
T76	0	3678	0	0
T77	0	4430	0	0
T78	0	3944	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132171066	6497	0	0
T9	101465	0	0	0
T22	89168	218	0	0
T23	244463	0	0	0
T25	196997	0	0	0
T54	176206	0	0	0
T55	68092	0	0	0
T56	42264	0	0	0
T57	33538	0	0	0
T64	48269	0	0	0
T65	76522	0	0	0
T74	0	93	0	0
T76	0	233	0	0
T117	0	173	0	0
T118	0	243	0	0
T119	0	155	0	0
T120	0	345	0	0
T121	0	560	0	0
T122	0	346	0	0
T123	0	153	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132171066	5920	0	0
T9	101465	0	0	0
T22	89168	275	0	0
T23	244463	0	0	0
T25	196997	0	0	0
T54	176206	0	0	0
T55	68092	0	0	0
T56	42264	0	0	0
T57	33538	0	0	0
T64	48269	0	0	0
T65	76522	0	0	0
T74	0	42	0	0
T76	0	312	0	0
T117	0	191	0	0
T118	0	239	0	0
T119	0	164	0	0
T120	0	233	0	0
T121	0	375	0	0
T122	0	342	0	0
T123	0	114	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132171066	6633	0	0
T9	101465	0	0	0
T22	89168	306	0	0
T23	244463	0	0	0
T25	196997	0	0	0
T54	176206	0	0	0
T55	68092	0	0	0
T56	42264	0	0	0
T57	33538	0	0	0
T64	48269	0	0	0
T65	76522	0	0	0
T74	0	79	0	0
T76	0	327	0	0
T117	0	189	0	0
T118	0	274	0	0
T119	0	147	0	0
T120	0	373	0	0
T121	0	498	0	0
T122	0	353	0	0
T123	0	174	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132171066	4536	0	0
T9	101465	0	0	0
T22	89168	300	0	0
T23	244463	0	0	0
T25	196997	0	0	0
T54	176206	0	0	0
T55	68092	0	0	0
T56	42264	0	0	0
T57	33538	0	0	0
T64	48269	0	0	0
T65	76522	0	0	0
T74	0	40	0	0
T76	0	261	0	0
T117	0	121	0	0
T118	0	255	0	0
T119	0	108	0	0
T120	0	343	0	0
T121	0	555	0	0
T122	0	306	0	0
T123	0	132	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1132171066	3914	0	0
T9	101465	0	0	0
T22	89168	239	0	0
T23	244463	0	0	0
T25	196997	0	0	0
T54	176206	0	0	0
T55	68092	0	0	0
T56	42264	0	0	0
T57	33538	0	0	0
T64	48269	0	0	0
T65	76522	0	0	0
T74	0	27	0	0
T76	0	212	0	0
T117	0	128	0	0
T118	0	130	0	0
T119	0	135	0	0
T120	0	305	0	0
T121	0	349	0	0
T122	0	321	0	0
T123	0	171	0	0