Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16341101

1

T3

5876

T4

45

T7

477

full_word

153638377

1

T2

2597

T3

1333

T4

456

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	169979208	1			T2	2597		T3	7209		T4	501
auto[TlIntgErrCmd]	85	1			T63	6		T64	2		T65	7
auto[TlIntgErrData]	93	1			T63	6		T64	6		T65	7
auto[TlIntgErrBoth]	92	1			T63	8		T64	2		T65	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81989896

1

T2

1309

T3

3651

T4

243

auto[1]

87989582

1

T2

1288

T3

3558

T4

258

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7997354	1			T3	2947		T4	23		T7	253
auto[TlIntgErrNone]	partial	auto[1]	8343499	1			T3	2929		T4	22		T7	224
auto[TlIntgErrNone]	full_word	auto[0]	73992420	1			T2	1309		T3	704		T4	220
auto[TlIntgErrNone]	full_word	auto[1]	79645935	1			T2	1288		T3	629		T4	236
auto[TlIntgErrCmd]	partial	auto[0]	25	1			T63	2		T64	1		T65	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T63	4		T64	1		T65	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T136	1		T131	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T128	1		T135	1		T138	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T63	2		T64	3		T65	4
auto[TlIntgErrData]	partial	auto[1]	41	1			T63	3		T64	3		T65	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T63	1		T65	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T135	1		T139	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T63	2		T64	2		T65	4
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T63	6		T65	2		T129	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T138	1		T140	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T138	1		T134	1		T132	1