Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	737902	1			T9	5		T12	683		T5	15
auto[1]	10791409	1			T2	1306		T3	10		T7	2541
auto[2]	584748	1			T9	7		T12	617		T5	16
auto[3]	10497370	1			T2	1287		T3	10		T7	2430

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14289257	1			T2	2593		T7	4088		T9	10
auto[1]	2089571	1			T3	4		T7	438		T9	4
auto[2]	2142390	1			T7	414		T9	2		T10	1099
auto[3]	4090211	1			T3	16		T7	31		T10	253

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9223351

1

T2

2593

T3

20

T7

4971

auto[1]

13388078

1

T33

4

T53

187919

T55

194430

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	197387	1			T9	5		T12	567		T5	10
auto[0]	auto[0]	auto[1]	20743	1			T12	56		T5	3		T34	39
auto[0]	auto[0]	auto[2]	21162	1			T12	54		T5	2		T34	41
auto[0]	auto[0]	auto[3]	61404	1			T12	6		T34	163		T146	1
auto[0]	auto[1]	auto[0]	3384655	1			T2	1306		T7	2063		T10	2606
auto[0]	auto[1]	auto[1]	344981	1			T3	4		T7	228		T9	2
auto[0]	auto[1]	auto[2]	367273	1			T7	232		T10	563		T12	13
auto[0]	auto[1]	auto[3]	368203	1			T3	6		T7	18		T10	129
auto[0]	auto[2]	auto[0]	137523	1			T9	5		T12	525		T5	13
auto[0]	auto[2]	auto[1]	17699	1			T9	2		T12	52		T5	3
auto[0]	auto[2]	auto[2]	19913	1			T12	38		T34	32		T146	69
auto[0]	auto[2]	auto[3]	44126	1			T12	2		T34	143		T146	6
auto[0]	auto[3]	auto[0]	3205865	1			T2	1287		T7	2025		T10	2514
auto[0]	auto[3]	auto[1]	345973	1			T7	210		T10	535		T12	5
auto[0]	auto[3]	auto[2]	353437	1			T7	182		T9	2		T10	536
auto[0]	auto[3]	auto[3]	333007	1			T3	10		T7	13		T10	124
auto[1]	auto[0]	auto[0]	14500	1			T104	567		T105	486		T106	316
auto[1]	auto[0]	auto[1]	64908	1			T104	2569		T105	2035		T106	1356
auto[1]	auto[0]	auto[2]	64812	1			T104	2610		T105	2026		T106	1348
auto[1]	auto[0]	auto[3]	292986	1			T104	11830		T105	9396		T106	6095
auto[1]	auto[1]	auto[0]	3671030	1			T53	77781		T55	80279		T104	107
auto[1]	auto[1]	auto[1]	643808	1			T53	7756		T55	8169		T104	2541
auto[1]	auto[1]	auto[2]	624336	1			T53	7673		T55	8058		T104	461
auto[1]	auto[1]	auto[3]	1387123	1			T33	2		T53	736		T55	822
auto[1]	auto[2]	auto[0]	10243	1			T104	513		T105	300		T106	245
auto[1]	auto[2]	auto[1]	46113	1			T104	2377		T105	1196		T106	1252
auto[1]	auto[2]	auto[2]	56224	1			T104	1646		T105	1934		T106	1151
auto[1]	auto[2]	auto[3]	252907	1			T104	7920		T105	8985		T106	5090
auto[1]	auto[3]	auto[0]	3668054	1			T53	77691		T55	80206		T104	60
auto[1]	auto[3]	auto[1]	605346	1			T53	7720		T55	8066		T104	253
auto[1]	auto[3]	auto[2]	635233	1			T53	7764		T55	8031		T104	1762
auto[1]	auto[3]	auto[3]	1350455	1			T33	2		T53	798		T55	799