Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1205982466	239947	0	0
ctrl_regwen_rd_A	1205982466	5330	0	0
exec_rd_A	1205982466	4680	0	0
exec_regwen_rd_A	1205982466	5303	0	0
readback_rd_A	1205982466	3419	0	0
readback_regwen_rd_A	1205982466	3216	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1205982466	239947	0	0
T5	529890	0	0	0
T6	567154	0	0	0
T12	85478	2371	0	0
T20	0	7625	0	0
T22	33970	0	0	0
T23	160501	6562	0	0
T24	0	2687	0	0
T27	74698	0	0	0
T28	70895	0	0	0
T32	75633	0	0	0
T33	159875	0	0	0
T34	96188	0	0	0
T40	0	6643	0	0
T51	0	6644	0	0
T58	0	11613	0	0
T59	0	10587	0	0
T67	0	2448	0	0
T70	0	1831	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1205982466	5330	0	0
T40	180379	469	0	0
T48	0	356	0	0
T56	269307	0	0	0
T58	0	924	0	0
T88	112213	0	0	0
T96	177695	0	0	0
T113	0	110	0	0
T114	0	227	0	0
T115	0	397	0	0
T116	0	116	0	0
T117	0	188	0	0
T118	0	71	0	0
T119	0	264	0	0
T120	106317	0	0	0
T121	72696	0	0	0
T122	516818	0	0	0
T123	75383	0	0	0
T124	33802	0	0	0
T125	232780	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1205982466	4680	0	0
T40	180379	308	0	0
T48	0	341	0	0
T56	269307	0	0	0
T58	0	675	0	0
T88	112213	0	0	0
T96	177695	0	0	0
T113	0	97	0	0
T114	0	218	0	0
T115	0	397	0	0
T116	0	106	0	0
T117	0	156	0	0
T118	0	56	0	0
T119	0	175	0	0
T120	106317	0	0	0
T121	72696	0	0	0
T122	516818	0	0	0
T123	75383	0	0	0
T124	33802	0	0	0
T125	232780	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1205982466	5303	0	0
T40	180379	422	0	0
T48	0	450	0	0
T56	269307	0	0	0
T58	0	876	0	0
T88	112213	0	0	0
T96	177695	0	0	0
T113	0	144	0	0
T114	0	291	0	0
T115	0	408	0	0
T116	0	106	0	0
T117	0	188	0	0
T118	0	83	0	0
T119	0	216	0	0
T120	106317	0	0	0
T121	72696	0	0	0
T122	516818	0	0	0
T123	75383	0	0	0
T124	33802	0	0	0
T125	232780	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1205982466	3419	0	0
T40	180379	423	0	0
T48	0	321	0	0
T56	269307	0	0	0
T58	0	846	0	0
T88	112213	0	0	0
T96	177695	0	0	0
T113	0	104	0	0
T114	0	259	0	0
T115	0	409	0	0
T116	0	103	0	0
T117	0	202	0	0
T118	0	55	0	0
T119	0	208	0	0
T120	106317	0	0	0
T121	72696	0	0	0
T122	516818	0	0	0
T123	75383	0	0	0
T124	33802	0	0	0
T125	232780	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1205982466	3216	0	0
T40	180379	353	0	0
T48	0	330	0	0
T56	269307	0	0	0
T58	0	841	0	0
T88	112213	0	0	0
T96	177695	0	0	0
T113	0	76	0	0
T114	0	214	0	0
T115	0	386	0	0
T116	0	66	0	0
T117	0	219	0	0
T118	0	64	0	0
T119	0	168	0	0
T120	106317	0	0	0
T121	72696	0	0	0
T122	516818	0	0	0
T123	75383	0	0	0
T124	33802	0	0	0
T125	232780	0	0	0