Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16497692

1

T3

100

T4

103

T5

598

full_word

164449801

1

T3

908

T4

960

T5

119

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180947183	1			T3	1008		T4	1063		T5	717
auto[TlIntgErrCmd]	107	1			T60	8		T61	3		T62	1
auto[TlIntgErrData]	109	1			T61	3		T62	3		T115	12
auto[TlIntgErrBoth]	94	1			T60	2		T61	4		T62	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87536994

1

T3

528

T4

507

T5

367

auto[1]

93410499

1

T3

480

T4

556

T5

350

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8074504	1			T3	42		T4	56		T5	306
auto[TlIntgErrNone]	partial	auto[1]	8422904	1			T3	58		T4	47		T5	292
auto[TlIntgErrNone]	full_word	auto[0]	79462350	1			T3	486		T4	451		T5	61
auto[TlIntgErrNone]	full_word	auto[1]	84987425	1			T3	422		T4	509		T5	58
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T60	1		T115	4		T119	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T60	7		T61	3		T119	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T122	1		T114	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T62	1		T119	1		T123	3
auto[TlIntgErrData]	partial	auto[0]	47	1			T61	1		T62	2		T115	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T61	1		T62	1		T115	6
auto[TlIntgErrData]	full_word	auto[0]	4	1			T61	1		T115	2		T119	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T124	1		T123	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T60	1		T61	3		T62	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T60	1		T62	3		T115	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T61	1		T123	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T62	1		T115	1		T125	1