Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	945681	1			T5	1		T14	594		T33	2
auto[1]	11047346	1			T5	2		T8	375		T14	123
auto[2]	737268	1			T5	1		T14	507		T33	3
auto[3]	10773475	1			T5	1		T8	380		T14	89

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15028387	1			T8	640		T14	1026		T33	5
auto[1]	2201687	1			T8	53		T14	133		T33	1
auto[2]	2241460	1			T8	59		T14	133		T33	2
auto[3]	4032236	1			T5	5		T8	3		T14	21

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9993319

1

T5

5

T8

755

T14

1313

auto[1]

13510451

1

T35

1

T57

1

T58

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	500012	1			T14	500		T33	2		T10	18
auto[0]	auto[0]	auto[1]	50951	1			T14	48		T34	1		T53	86
auto[0]	auto[0]	auto[2]	50691	1			T14	41		T53	86		T139	1
auto[0]	auto[0]	auto[3]	48191	1			T5	1		T14	5		T34	2
auto[0]	auto[1]	auto[0]	3525330	1			T8	321		T14	62		T27	1173
auto[0]	auto[1]	auto[1]	374144	1			T8	22		T14	45		T33	1
auto[0]	auto[1]	auto[2]	370013	1			T8	30		T14	11		T33	1
auto[0]	auto[1]	auto[3]	268986	1			T5	2		T8	2		T14	5
auto[0]	auto[2]	auto[0]	376705	1			T14	424		T33	3		T10	20
auto[0]	auto[2]	auto[1]	40399	1			T14	38		T53	80		T11	1
auto[0]	auto[2]	auto[2]	39291	1			T14	39		T34	1		T10	2
auto[0]	auto[2]	auto[3]	36873	1			T5	1		T14	6		T34	1
auto[0]	auto[3]	auto[0]	3347001	1			T8	319		T14	40		T27	1107
auto[0]	auto[3]	auto[1]	348890	1			T8	31		T14	2		T27	257
auto[0]	auto[3]	auto[2]	371828	1			T8	29		T14	42		T33	1
auto[0]	auto[3]	auto[3]	244014	1			T5	1		T8	1		T14	5
auto[1]	auto[0]	auto[0]	9654	1			T138	148		T140	639		T141	94
auto[1]	auto[0]	auto[1]	43904	1			T138	687		T140	2898		T141	468
auto[1]	auto[0]	auto[2]	44081	1			T138	663		T140	2795		T141	507
auto[1]	auto[0]	auto[3]	198197	1			T82	2		T138	3042		T140	13039
auto[1]	auto[1]	auto[0]	3633402	1			T57	1		T59	48225		T142	1
auto[1]	auto[1]	auto[1]	672976	1			T59	4296		T97	6990		T98	3359
auto[1]	auto[1]	auto[2]	659637	1			T59	4858		T97	6797		T98	3754
auto[1]	auto[1]	auto[3]	1542858	1			T59	413		T97	31563		T98	352
auto[1]	auto[2]	auto[0]	6109	1			T140	645		T143	1002		T144	548
auto[1]	auto[2]	auto[1]	27276	1			T140	2582		T143	4747		T144	2533
auto[1]	auto[2]	auto[2]	38363	1			T138	641		T140	1952		T141	412
auto[1]	auto[2]	auto[3]	172252	1			T138	2686		T140	8661		T141	1910
auto[1]	auto[3]	auto[0]	3630174	1			T35	1		T59	48296		T97	1466
auto[1]	auto[3]	auto[1]	643147	1			T59	4793		T97	7016		T98	3703
auto[1]	auto[3]	auto[2]	667556	1			T59	4281		T97	7044		T98	3322
auto[1]	auto[3]	auto[3]	1520865	1			T58	2		T59	433		T97	31593