Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1230645164	246654	0	0
ctrl_regwen_rd_A	1230645164	2971	0	0
exec_rd_A	1230645164	2956	0	0
exec_regwen_rd_A	1230645164	3392	0	0
readback_rd_A	1230645164	1626	0	0
readback_regwen_rd_A	1230645164	1391	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230645164	246654	0	0
T7	22661	1657	0	0
T8	35455	0	0	0
T14	94107	0	0	0
T21	0	757	0	0
T22	0	5176	0	0
T24	0	5595	0	0
T25	98201	0	0	0
T26	71808	0	0	0
T27	70768	0	0	0
T29	72097	0	0	0
T30	34520	0	0	0
T33	116643	0	0	0
T34	146946	0	0	0
T37	0	3435	0	0
T50	0	14363	0	0
T55	0	4758	0	0
T56	0	10307	0	0
T65	0	3803	0	0
T66	0	6519	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230645164	2971	0	0
T6	17669	0	0	0
T9	628412	0	0	0
T15	1055	0	0	0
T21	11921	64	0	0
T22	92559	0	0	0
T28	73108	0	0	0
T35	74063	0	0	0
T36	67951	0	0	0
T37	0	198	0	0
T41	139432	0	0	0
T51	78099	0	0	0
T105	0	139	0	0
T106	0	355	0	0
T107	0	98	0	0
T108	0	50	0	0
T109	0	273	0	0
T110	0	215	0	0
T111	0	105	0	0
T112	0	30	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230645164	2956	0	0
T6	17669	0	0	0
T9	628412	0	0	0
T15	1055	0	0	0
T21	11921	45	0	0
T22	92559	0	0	0
T28	73108	0	0	0
T35	74063	0	0	0
T36	67951	0	0	0
T37	0	251	0	0
T41	139432	0	0	0
T51	78099	0	0	0
T105	0	115	0	0
T106	0	384	0	0
T107	0	75	0	0
T108	0	75	0	0
T109	0	259	0	0
T110	0	144	0	0
T111	0	124	0	0
T112	0	15	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230645164	3392	0	0
T6	17669	0	0	0
T9	628412	0	0	0
T15	1055	0	0	0
T21	11921	31	0	0
T22	92559	0	0	0
T28	73108	0	0	0
T35	74063	0	0	0
T36	67951	0	0	0
T37	0	295	0	0
T41	139432	0	0	0
T51	78099	0	0	0
T105	0	146	0	0
T106	0	568	0	0
T107	0	71	0	0
T108	0	91	0	0
T109	0	175	0	0
T110	0	173	0	0
T111	0	132	0	0
T112	0	22	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230645164	1626	0	0
T6	17669	0	0	0
T9	628412	0	0	0
T15	1055	0	0	0
T21	11921	17	0	0
T22	92559	0	0	0
T28	73108	0	0	0
T35	74063	0	0	0
T36	67951	0	0	0
T37	0	242	0	0
T41	139432	0	0	0
T51	78099	0	0	0
T105	0	89	0	0
T106	0	495	0	0
T107	0	37	0	0
T108	0	84	0	0
T109	0	165	0	0
T110	0	134	0	0
T111	0	99	0	0
T112	0	66	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1230645164	1391	0	0
T6	17669	0	0	0
T9	628412	0	0	0
T15	1055	0	0	0
T21	11921	44	0	0
T22	92559	0	0	0
T28	73108	0	0	0
T35	74063	0	0	0
T36	67951	0	0	0
T37	0	173	0	0
T41	139432	0	0	0
T51	78099	0	0	0
T105	0	86	0	0
T106	0	362	0	0
T107	0	52	0	0
T108	0	47	0	0
T109	0	210	0	0
T110	0	98	0	0
T111	0	78	0	0
T112	0	53	0	0