Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15439740

1

T1

437

T2

2276

T4

86

full_word

159542258

1

T1

4615

T2

518

T3

2502

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	174981708	1			T1	5052		T2	2794		T3	2502
auto[TlIntgErrCmd]	108	1			T68	6		T69	2		T70	5
auto[TlIntgErrData]	112	1			T68	13		T69	4		T70	8
auto[TlIntgErrBoth]	70	1			T68	1		T69	4		T70	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84477725

1

T1

2579

T2

1395

T3

1303

auto[1]

90504273

1

T1

2473

T2

1399

T3

1199

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7545616	1			T1	226		T2	1129		T4	41
auto[TlIntgErrNone]	partial	auto[1]	7893860	1			T1	211		T2	1147		T4	45
auto[TlIntgErrNone]	full_word	auto[0]	76931969	1			T1	2353		T2	266		T3	1303
auto[TlIntgErrNone]	full_word	auto[1]	82610263	1			T1	2262		T2	252		T3	1199
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T68	3		T69	2		T70	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T68	3		T70	2		T142	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T143	1		T144	2		T145	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T146	1		T147	1		T145	2
auto[TlIntgErrData]	partial	auto[0]	47	1			T68	8		T69	1		T70	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T68	4		T69	3		T70	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T143	1		T144	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T68	1		T149	1		T150	2
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T68	1		T69	2		T70	2
auto[TlIntgErrBoth]	partial	auto[1]	31	1			T69	2		T70	5		T151	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T144	1		T148	1		T152	1