Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	745756	1			T2	2		T5	16		T23	153
auto[1]	10019156	1			T1	2		T3	1303		T5	5
auto[2]	558111	1			T2	1		T5	9		T23	114
auto[3]	9742379	1			T2	2		T3	1198		T5	1

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13684662	1			T1	1		T3	2501		T5	26
auto[1]	1937950	1			T1	1		T2	1		T5	3
auto[2]	1972836	1			T2	1		T5	1		T23	45
auto[3]	3469954	1			T2	3		T5	1		T23	3

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7946492

1

T1

2

T2

5

T3

2501

auto[1]

13118910

1

T53

2

T56

1

T66

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	221462	1			T5	13		T23	128		T35	4
auto[0]	auto[0]	auto[1]	23670	1			T2	1		T5	2		T23	13
auto[0]	auto[0]	auto[2]	23606	1			T2	1		T5	1		T23	12
auto[0]	auto[0]	auto[3]	66595	1			T166	1		T167	391		T95	70
auto[0]	auto[1]	auto[0]	2934278	1			T1	1		T3	1303		T5	3
auto[0]	auto[1]	auto[1]	300686	1			T1	1		T5	1		T23	17
auto[0]	auto[1]	auto[2]	307510	1			T23	5		T31	216		T33	328
auto[0]	auto[1]	auto[3]	240032	1			T5	1		T31	50		T33	77
auto[0]	auto[2]	auto[0]	146618	1			T5	9		T23	90		T19	24
auto[0]	auto[2]	auto[1]	18678	1			T23	8		T90	11		T167	69
auto[0]	auto[2]	auto[2]	21393	1			T23	14		T35	2		T90	12
auto[0]	auto[2]	auto[3]	46586	1			T2	1		T23	2		T54	1
auto[0]	auto[3]	auto[0]	2787556	1			T3	1198		T5	1		T23	27
auto[0]	auto[3]	auto[1]	290348	1			T23	1		T31	248		T33	296
auto[0]	auto[3]	auto[2]	305827	1			T23	14		T31	249		T33	296
auto[0]	auto[3]	auto[3]	211647	1			T2	2		T23	1		T31	66
auto[1]	auto[0]	auto[0]	13321	1			T123	76		T128	610		T168	889
auto[1]	auto[0]	auto[1]	60806	1			T123	353		T128	2917		T168	3981
auto[1]	auto[0]	auto[2]	61071	1			T123	353		T128	2818		T168	3909
auto[1]	auto[0]	auto[3]	275225	1			T67	2		T105	3		T123	1552
auto[1]	auto[1]	auto[0]	3791663	1			T53	1		T66	1		T117	1822
auto[1]	auto[1]	auto[1]	620958	1			T117	8442		T123	1322		T124	6230
auto[1]	auto[1]	auto[2]	594829	1			T117	8321		T123	700		T124	6464
auto[1]	auto[1]	auto[3]	1229200	1			T67	1		T117	38161		T104	3
auto[1]	auto[2]	auto[0]	9830	1			T128	614		T169	1		T168	780
auto[1]	auto[2]	auto[1]	43989	1			T128	2607		T168	3666		T170	1875
auto[1]	auto[2]	auto[2]	49339	1			T123	336		T128	2429		T168	2616
auto[1]	auto[2]	auto[3]	221678	1			T123	1471		T128	10672		T107	1
auto[1]	auto[3]	auto[0]	3779934	1			T53	1		T56	1		T117	1907
auto[1]	auto[3]	auto[1]	578815	1			T117	8313		T123	333		T124	6345
auto[1]	auto[3]	auto[2]	609261	1			T117	8317		T123	1276		T124	6411
auto[1]	auto[3]	auto[3]	1178991	1			T117	37713		T104	2		T123	5594