Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1223127454	250618	0	0
ctrl_regwen_rd_A	1223127454	3232	0	0
exec_rd_A	1223127454	2865	0	0
exec_regwen_rd_A	1223127454	3135	0	0
readback_rd_A	1223127454	2181	0	0
readback_regwen_rd_A	1223127454	1827	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223127454	250618	0	0
T6	39226	0	0	0
T13	24040	1197	0	0
T14	976	0	0	0
T15	11871	0	0	0
T22	1009	0	0	0
T23	80561	0	0	0
T24	64741	3130	0	0
T25	0	5385	0	0
T28	34385	0	0	0
T31	70324	0	0	0
T42	0	4039	0	0
T51	0	13438	0	0
T65	0	2166	0	0
T73	0	1820	0	0
T74	0	6022	0	0
T75	0	2619	0	0
T76	0	1784	0	0
T77	33577	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223127454	3232	0	0
T24	64741	264	0	0
T25	83472	0	0	0
T29	78825	0	0	0
T32	147546	0	0	0
T33	71259	0	0	0
T34	78321	0	0	0
T35	39600	0	0	0
T36	132367	0	0	0
T42	0	121	0	0
T73	0	109	0	0
T76	0	156	0	0
T89	46864	0	0	0
T135	0	457	0	0
T136	0	178	0	0
T137	0	147	0	0
T138	0	61	0	0
T139	0	53	0	0
T140	0	660	0	0
T141	67754	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223127454	2865	0	0
T24	64741	249	0	0
T25	83472	0	0	0
T29	78825	0	0	0
T32	147546	0	0	0
T33	71259	0	0	0
T34	78321	0	0	0
T35	39600	0	0	0
T36	132367	0	0	0
T42	0	99	0	0
T73	0	97	0	0
T76	0	181	0	0
T89	46864	0	0	0
T135	0	348	0	0
T136	0	88	0	0
T137	0	149	0	0
T138	0	76	0	0
T139	0	47	0	0
T140	0	586	0	0
T141	67754	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223127454	3135	0	0
T24	64741	199	0	0
T25	83472	0	0	0
T29	78825	0	0	0
T32	147546	0	0	0
T33	71259	0	0	0
T34	78321	0	0	0
T35	39600	0	0	0
T36	132367	0	0	0
T42	0	118	0	0
T73	0	179	0	0
T76	0	173	0	0
T89	46864	0	0	0
T135	0	405	0	0
T136	0	96	0	0
T137	0	113	0	0
T138	0	126	0	0
T139	0	60	0	0
T140	0	667	0	0
T141	67754	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223127454	2181	0	0
T24	64741	143	0	0
T25	83472	0	0	0
T29	78825	0	0	0
T32	147546	0	0	0
T33	71259	0	0	0
T34	78321	0	0	0
T35	39600	0	0	0
T36	132367	0	0	0
T42	0	146	0	0
T73	0	145	0	0
T76	0	65	0	0
T89	46864	0	0	0
T135	0	363	0	0
T136	0	114	0	0
T137	0	95	0	0
T138	0	49	0	0
T139	0	46	0	0
T140	0	664	0	0
T141	67754	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1223127454	1827	0	0
T24	64741	135	0	0
T25	83472	0	0	0
T29	78825	0	0	0
T32	147546	0	0	0
T33	71259	0	0	0
T34	78321	0	0	0
T35	39600	0	0	0
T36	132367	0	0	0
T42	0	112	0	0
T73	0	124	0	0
T76	0	118	0	0
T89	46864	0	0	0
T135	0	297	0	0
T136	0	100	0	0
T137	0	141	0	0
T138	0	33	0	0
T139	0	39	0	0
T140	0	461	0	0
T141	67754	0	0	0