Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16124651

1

T1

15

T3

13

T8

4134

full_word

141719656

1

T1

159

T2

261

T3

91

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	157844007	1			T1	174		T2	261		T3	104
auto[TlIntgErrCmd]	109	1			T57	6		T58	3		T59	9
auto[TlIntgErrData]	100	1			T57	10		T58	3		T59	5
auto[TlIntgErrBoth]	91	1			T57	4		T58	4		T59	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75953337

1

T1

77

T2

130

T3

52

auto[1]

81890970

1

T1

97

T2

131

T3

52

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7897892	1			T1	6		T3	4		T8	2042
auto[TlIntgErrNone]	partial	auto[1]	8226486	1			T1	9		T3	9		T8	2092
auto[TlIntgErrNone]	full_word	auto[0]	68055307	1			T1	71		T2	130		T3	48
auto[TlIntgErrNone]	full_word	auto[1]	73664322	1			T1	88		T2	131		T3	43
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T57	2		T59	6		T118	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T57	3		T58	3		T59	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T57	1		T59	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T59	1		T118	1		T121	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T57	3		T59	4		T118	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T57	5		T58	3		T59	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T57	1		T116	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T57	1		T114	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T57	1		T58	3		T59	3
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T57	2		T58	1		T59	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T57	1		T124	2		T125	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T59	1		T117	1		T120	1