Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	995487	1			T4	12		T6	1		T55	4681
auto[1]	10595306	1			T1	3		T2	127		T3	51
auto[2]	775182	1			T8	2		T4	6		T6	3
auto[3]	10269332	1			T2	130		T3	51		T8	3

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14508585	1			T1	2		T2	257		T3	67
auto[1]	2084161	1			T1	1		T3	22		T4	4
auto[2]	2120501	1			T3	12		T8	1		T4	4
auto[3]	3922060	1			T3	1		T8	9		T4	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9527556

1

T1

3

T2

257

T3

102

auto[1]

13107751

1

T32

144496

T55

33097

T56

186776

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	380160	1			T4	8		T6	1		T134	36
auto[0]	auto[0]	auto[1]	40046	1			T4	1		T134	141		T77	8
auto[0]	auto[0]	auto[2]	39902	1			T4	2		T134	114		T77	7
auto[0]	auto[0]	auto[3]	74787	1			T4	1		T134	553		T77	46
auto[0]	auto[1]	auto[0]	3354350	1			T1	2		T2	127		T3	33
auto[0]	auto[1]	auto[1]	352447	1			T1	1		T3	14		T4	1
auto[0]	auto[1]	auto[2]	359917	1			T3	3		T8	1		T4	1
auto[0]	auto[1]	auto[3]	353530	1			T3	1		T8	4		T34	1
auto[0]	auto[2]	auto[0]	276733	1			T4	3		T6	3		T134	20
auto[0]	auto[2]	auto[1]	33145	1			T4	2		T134	113		T78	18
auto[0]	auto[2]	auto[2]	30804	1			T4	1		T134	119		T77	8
auto[0]	auto[2]	auto[3]	56017	1			T8	2		T134	474		T77	31
auto[0]	auto[3]	auto[0]	3161106	1			T2	130		T3	34		T32	11
auto[0]	auto[3]	auto[1]	338991	1			T3	8		T32	1		T27	1704
auto[0]	auto[3]	auto[2]	356576	1			T3	9		T32	1		T27	1704
auto[0]	auto[3]	auto[3]	319045	1			T8	3		T34	2		T27	170
auto[1]	auto[0]	auto[0]	15188	1			T55	171		T103	127		T135	100
auto[1]	auto[0]	auto[1]	68512	1			T55	705		T103	526		T135	427
auto[1]	auto[0]	auto[2]	68263	1			T55	711		T103	535		T135	461
auto[1]	auto[0]	auto[3]	308629	1			T55	3094		T103	2293		T87	2
auto[1]	auto[1]	auto[0]	3658408	1			T32	59693		T55	317		T56	77070
auto[1]	auto[1]	auto[1]	622991	1			T32	5871		T55	2113		T56	7678
auto[1]	auto[1]	auto[2]	594962	1			T32	6061		T55	1316		T56	7637
auto[1]	auto[1]	auto[3]	1298701	1			T32	553		T55	9459		T56	758
auto[1]	auto[2]	auto[0]	11200	1			T136	343		T137	1323		T138	636
auto[1]	auto[2]	auto[1]	50758	1			T136	1557		T129	1		T137	5650
auto[1]	auto[2]	auto[2]	57641	1			T55	644		T103	509		T135	349
auto[1]	auto[2]	auto[3]	258884	1			T55	2772		T103	2166		T88	1
auto[1]	auto[3]	auto[0]	3651440	1			T32	59749		T55	106		T56	77181
auto[1]	auto[3]	auto[1]	577271	1			T32	5989		T55	589		T56	7866
auto[1]	auto[3]	auto[2]	612436	1			T32	5978		T55	2046		T56	7881
auto[1]	auto[3]	auto[3]	1252467	1			T32	602		T55	9054		T56	705