Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1031561884	212930	0	0
ctrl_regwen_rd_A	1031561884	5930	0	0
exec_rd_A	1031561884	5777	0	0
exec_regwen_rd_A	1031561884	5816	0	0
readback_rd_A	1031561884	3681	0	0
readback_regwen_rd_A	1031561884	3106	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031561884	212930	0	0
T5	36408	0	0	0
T10	164923	6242	0	0
T11	1235	0	0	0
T12	141259	0	0	0
T23	0	939	0	0
T24	0	1329	0	0
T25	0	5145	0	0
T27	284480	0	0	0
T32	267805	0	0	0
T33	540583	0	0	0
T34	41320	0	0	0
T35	74939	0	0	0
T36	525746	0	0	0
T49	0	10400	0	0
T51	0	7392	0	0
T52	0	6017	0	0
T63	0	982	0	0
T64	0	4087	0	0
T65	0	8245	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031561884	5930	0	0
T5	36408	0	0	0
T10	164923	484	0	0
T11	1235	0	0	0
T12	141259	0	0	0
T23	0	70	0	0
T24	0	79	0	0
T27	284480	0	0	0
T32	267805	0	0	0
T33	540583	0	0	0
T34	41320	0	0	0
T35	74939	0	0	0
T36	525746	0	0	0
T63	0	60	0	0
T64	0	203	0	0
T108	0	95	0	0
T109	0	120	0	0
T110	0	80	0	0
T111	0	69	0	0
T112	0	396	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031561884	5777	0	0
T5	36408	0	0	0
T10	164923	401	0	0
T11	1235	0	0	0
T12	141259	0	0	0
T23	0	55	0	0
T24	0	84	0	0
T27	284480	0	0	0
T32	267805	0	0	0
T33	540583	0	0	0
T34	41320	0	0	0
T35	74939	0	0	0
T36	525746	0	0	0
T63	0	52	0	0
T64	0	172	0	0
T108	0	63	0	0
T109	0	157	0	0
T110	0	120	0	0
T111	0	61	0	0
T112	0	464	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031561884	5816	0	0
T5	36408	0	0	0
T10	164923	531	0	0
T11	1235	0	0	0
T12	141259	0	0	0
T23	0	95	0	0
T24	0	68	0	0
T27	284480	0	0	0
T32	267805	0	0	0
T33	540583	0	0	0
T34	41320	0	0	0
T35	74939	0	0	0
T36	525746	0	0	0
T63	0	23	0	0
T64	0	152	0	0
T108	0	112	0	0
T109	0	236	0	0
T110	0	86	0	0
T111	0	121	0	0
T112	0	372	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031561884	3681	0	0
T5	36408	0	0	0
T10	164923	445	0	0
T11	1235	0	0	0
T12	141259	0	0	0
T23	0	69	0	0
T24	0	145	0	0
T27	284480	0	0	0
T32	267805	0	0	0
T33	540583	0	0	0
T34	41320	0	0	0
T35	74939	0	0	0
T36	525746	0	0	0
T63	0	38	0	0
T64	0	162	0	0
T108	0	87	0	0
T109	0	135	0	0
T110	0	55	0	0
T111	0	54	0	0
T112	0	430	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031561884	3106	0	0
T5	36408	0	0	0
T10	164923	394	0	0
T11	1235	0	0	0
T12	141259	0	0	0
T23	0	90	0	0
T24	0	95	0	0
T27	284480	0	0	0
T32	267805	0	0	0
T33	540583	0	0	0
T34	41320	0	0	0
T35	74939	0	0	0
T36	525746	0	0	0
T63	0	32	0	0
T64	0	120	0	0
T108	0	127	0	0
T109	0	202	0	0
T110	0	49	0	0
T111	0	57	0	0
T112	0	347	0	0