Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	387820322	1			T3	2026		T4	15164		T5	5842
instr_valid_dis	342123418	1			T3	2026		T4	15164		T5	5842
instr_en	35156621	1			T17	21752		T28	96320		T41	61514

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	13465366	1			T27	42		T28	45456		T18	1938
sram_ifetch_valid_disable	342932316	1			T3	2026		T4	15164		T5	5842
sram_ifetch_enable	31422640	1			T17	56636		T27	115848		T28	70520

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	387820322	1			T3	2026		T4	15164		T5	5842
hw_debug_en_valid_off	345089986	1			T3	2026		T4	15164		T5	5842
hw_debug_en_on	25093950	1			T27	96242		T28	80862		T18	93386

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	342932316	1			T3	2026		T4	15164		T5	5842
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	326235270	1			T3	2026		T4	15164		T5	5842
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12777965	1			T28	32858		T138	49216		T42	14998
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6789128	1			T27	42		T28	3386		T41	62880
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1418046	1			T41	47594		T19	18086		T147	37318
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4669700	1			T28	3386		T41	15286		T42	630
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4260662	1			T28	29076		T18	1938		T41	16752
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1805168	1			T28	29076		T18	1938		T64	55290
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1757188	1			T41	16752		T42	24964		T140	54810
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9037790	1			T27	61820		T28	51786		T18	56556
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3380698	1			T28	18928		T18	56556		T41	20494
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3826074	1			T28	32858		T138	18820		T42	14998

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	14859066	1			T17	21752		T28	60076		T41	29476
lc_exec_en	11795498	1			T27	34422		T18	34892		T41	18300
valid_exec_dis	335315318	1			T3	2026		T4	15164		T5	5842
invalid_exec_dis	44888006	1			T17	56636		T27	115890		T28	115976