Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.92 99.17 94.27 99.72 100.00 95.89 99.13 97.26


Total tests in report: 1040
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.82 61.82 90.61 90.61 60.78 60.78 49.72 49.72 23.81 23.81 77.70 77.70 93.03 93.03 37.11 37.11 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.582472791
88.41 26.59 96.81 6.20 81.99 21.21 90.98 41.25 90.48 66.67 89.71 12.01 95.07 2.03 73.86 36.75 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.696544689
91.70 3.29 98.41 1.59 85.19 3.20 93.60 2.62 100.00 9.52 93.14 3.43 96.08 1.02 75.50 1.65 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.526067104
93.03 1.33 98.66 0.25 87.80 2.61 94.49 0.90 100.00 0.00 94.85 1.72 96.08 0.00 79.34 3.84 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2501197079
94.02 0.99 98.83 0.17 89.22 1.42 96.07 1.58 100.00 0.00 95.83 0.98 96.08 0.00 82.08 2.74 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2810803129
94.82 0.81 98.83 0.00 89.57 0.36 96.07 0.00 100.00 0.00 95.83 0.00 96.08 0.00 87.39 5.30 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.581570570
95.52 0.69 99.08 0.25 89.57 0.00 96.07 0.00 100.00 0.00 96.08 0.25 96.23 0.15 91.59 4.20 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1429708918
96.13 0.61 99.08 0.00 90.28 0.71 98.21 2.13 100.00 0.00 96.08 0.00 96.95 0.73 92.32 0.73 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2351236169
96.43 0.30 99.08 0.00 90.28 0.00 98.48 0.28 100.00 0.00 96.08 0.00 96.95 0.00 94.15 1.83 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1888771088
96.64 0.21 99.08 0.00 90.52 0.24 98.48 0.00 100.00 0.00 96.08 0.00 97.97 1.02 94.33 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2113213717
96.82 0.18 99.08 0.00 90.52 0.00 98.48 0.00 100.00 0.00 96.08 0.00 97.97 0.00 95.61 1.28 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.681303623
96.95 0.13 99.16 0.08 90.52 0.00 99.31 0.83 100.00 0.00 96.08 0.00 97.97 0.00 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.676428936
97.07 0.12 99.16 0.00 90.52 0.00 99.31 0.00 100.00 0.00 96.08 0.00 98.84 0.87 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1728286515
97.15 0.08 99.16 0.00 90.52 0.00 99.31 0.00 100.00 0.00 96.08 0.00 98.84 0.00 96.16 0.55 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.357577351
97.23 0.07 99.16 0.00 90.52 0.00 99.45 0.14 100.00 0.00 96.08 0.00 98.84 0.00 96.53 0.37 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2288252785
97.29 0.06 99.16 0.00 90.88 0.36 99.52 0.07 100.00 0.00 96.08 0.00 98.84 0.00 96.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.189363786
97.34 0.05 99.16 0.00 90.88 0.00 99.52 0.00 100.00 0.00 96.08 0.00 98.84 0.00 96.89 0.37 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.606397129
97.38 0.04 99.16 0.00 90.88 0.00 99.52 0.00 100.00 0.00 96.08 0.00 99.13 0.29 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.942305492
97.41 0.03 99.16 0.00 90.88 0.00 99.52 0.00 100.00 0.00 96.08 0.00 99.13 0.00 97.07 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2629315349
97.43 0.03 99.16 0.00 90.88 0.00 99.52 0.00 100.00 0.00 96.08 0.00 99.13 0.00 97.26 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2883453118
97.45 0.02 99.16 0.00 90.88 0.00 99.66 0.14 100.00 0.00 96.08 0.00 99.13 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.127893119
97.47 0.02 99.16 0.00 91.00 0.12 99.66 0.00 100.00 0.00 96.08 0.00 99.13 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2560442736
97.48 0.01 99.16 0.00 91.00 0.00 99.72 0.07 100.00 0.00 96.08 0.00 99.13 0.00 97.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1661030894

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2987491046
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3889798075
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2112548885
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2648519941
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1583889077
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.235703208
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.258908047
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.471879878
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3100457051
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.987647936
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.367743418
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.252546890
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3552880199
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1948509682
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1929507998
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1158317490
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.962544626
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2804877765
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1468412791
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2378214328
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3181194121
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3873442079
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2026878553
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1099392151
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1003806082
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2955912359
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2372766026
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.399788646
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3633840755
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2644589557
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1909511309
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3861029916
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.70087532
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1035811864
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.732788089
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4219512913
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2066321105
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1247772426
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1738160476
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1370947280
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.722128387
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3805185444
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1149774604
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.427455095
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2445558556
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2071440242
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.864911912
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4216997540
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1988223326
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3681047781
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2581251644
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.325184819
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3172197963
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2983907056
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1240822452
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1262734279
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.156119168
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2662633633
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1529819238
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.8703782
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1197352291
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2750239490
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3883614282
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3432123348
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.371643389
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2970789548
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1087982391
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3133047548
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2446876047
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2567434424
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1754989099
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1637633120
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2083940181
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.331833815
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2972362463
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3042703715
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.732304785
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2982568500
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2068564635
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.48427173
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3768364122
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2549910958
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.111015360
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.61527984
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3896237762
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/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2743992749
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.428033804
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.24085956
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2712335747
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2462678732
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1687815898
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1241451840
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1233669355
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3262281914
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/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3687040293
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/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1745822202
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1162602891
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1108244619
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.669609358
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.204476976
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2651424341
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.446860310
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3678086660
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2640786318
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.496545056
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3186750929
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1324084615
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2266841927
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2360023954
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2504370697
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.293660304
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3498890267
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3597347289
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.1856296537
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.1477313854
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4006266038
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1543868598
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1616653351
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3047073835
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.302439909
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4098408853
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1287487221
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3918865914
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1373015288
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3054823043
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2693725587
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3679061756
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.278802305
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3153216945
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.65651748
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3834879972
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.265324548
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1671093107
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.4013831773
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2112627468
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.604729387
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3918024223
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2456271073
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.138432928
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3429310851
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.117771455
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2483545560
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.758142093
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3936148294
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3567702280
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1775439048
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1958286100
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3181318582
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2852870832
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.3054361116
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.4027071539
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1845718697
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3391123389
/workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1769841796



Total test records in report: 1040
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.431962838 Sep 18 10:01:19 AM UTC 24 Sep 18 10:01:20 AM UTC 24 114128042 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.676428936 Sep 18 10:01:16 AM UTC 24 Sep 18 10:01:22 AM UTC 24 683026295 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1661085990 Sep 18 10:01:18 AM UTC 24 Sep 18 10:01:24 AM UTC 24 663223429 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.1045583340 Sep 18 10:01:13 AM UTC 24 Sep 18 10:01:30 AM UTC 24 1983428177 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.2419479131 Sep 18 10:01:14 AM UTC 24 Sep 18 10:01:30 AM UTC 24 4119247398 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3521480909 Sep 18 10:01:15 AM UTC 24 Sep 18 10:01:32 AM UTC 24 1442682600 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.3626609400 Sep 18 10:01:32 AM UTC 24 Sep 18 10:01:37 AM UTC 24 345697598 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.526067104 Sep 18 10:01:38 AM UTC 24 Sep 18 10:01:42 AM UTC 24 402645997 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.189363786 Sep 18 10:01:42 AM UTC 24 Sep 18 10:01:45 AM UTC 24 39708400 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.582472791 Sep 18 10:01:24 AM UTC 24 Sep 18 10:01:45 AM UTC 24 747544173 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.4270223 Sep 18 10:01:30 AM UTC 24 Sep 18 10:01:47 AM UTC 24 699145555 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1584110272 Sep 18 10:01:49 AM UTC 24 Sep 18 10:02:02 AM UTC 24 695619470 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.2077951911 Sep 18 10:01:19 AM UTC 24 Sep 18 10:02:05 AM UTC 24 14842706965 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.895318946 Sep 18 10:01:46 AM UTC 24 Sep 18 10:02:07 AM UTC 24 2087018015 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.277317312 Sep 18 10:02:08 AM UTC 24 Sep 18 10:02:16 AM UTC 24 357100385 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2351236169 Sep 18 10:01:17 AM UTC 24 Sep 18 10:02:32 AM UTC 24 9293862882 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3184221807 Sep 18 10:02:00 AM UTC 24 Sep 18 10:02:34 AM UTC 24 1552361316 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.2736998335 Sep 18 10:01:31 AM UTC 24 Sep 18 10:02:35 AM UTC 24 6668108835 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1277569704 Sep 18 10:01:42 AM UTC 24 Sep 18 10:02:35 AM UTC 24 1482333379 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.397288920 Sep 18 10:01:15 AM UTC 24 Sep 18 10:02:35 AM UTC 24 1568494344 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2258612533 Sep 18 10:02:17 AM UTC 24 Sep 18 10:02:36 AM UTC 24 4726421363 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3737375633 Sep 18 10:02:35 AM UTC 24 Sep 18 10:02:37 AM UTC 24 15826904 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.3207993441 Sep 18 10:02:35 AM UTC 24 Sep 18 10:02:42 AM UTC 24 1618220485 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.709197583 Sep 18 10:01:26 AM UTC 24 Sep 18 10:02:43 AM UTC 24 761392057 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1840762970 Sep 18 10:02:35 AM UTC 24 Sep 18 10:02:51 AM UTC 24 770199604 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.696544689 Sep 18 10:01:37 AM UTC 24 Sep 18 10:03:07 AM UTC 24 8925341496 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2507996569 Sep 18 10:02:39 AM UTC 24 Sep 18 10:03:09 AM UTC 24 778541631 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1436567084 Sep 18 10:02:52 AM UTC 24 Sep 18 10:03:13 AM UTC 24 2796520037 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1728286515 Sep 18 10:01:17 AM UTC 24 Sep 18 10:03:21 AM UTC 24 2656825570 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2560442736 Sep 18 10:01:15 AM UTC 24 Sep 18 10:03:28 AM UTC 24 57961683047 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1368621080 Sep 18 10:03:26 AM UTC 24 Sep 18 10:03:33 AM UTC 24 1306774227 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.670327708 Sep 18 10:01:30 AM UTC 24 Sep 18 10:03:36 AM UTC 24 15068555650 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.26538221 Sep 18 10:02:01 AM UTC 24 Sep 18 10:03:42 AM UTC 24 50225053920 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3346723985 Sep 18 10:02:44 AM UTC 24 Sep 18 10:03:56 AM UTC 24 774063811 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.1123791723 Sep 18 10:02:15 AM UTC 24 Sep 18 10:03:57 AM UTC 24 2515357405 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.644900634 Sep 18 10:03:58 AM UTC 24 Sep 18 10:04:00 AM UTC 24 25673100 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.4062919679 Sep 18 10:03:57 AM UTC 24 Sep 18 10:04:00 AM UTC 24 100376356 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2883054351 Sep 18 10:01:16 AM UTC 24 Sep 18 10:04:09 AM UTC 24 7190116965 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1843821152 Sep 18 10:03:37 AM UTC 24 Sep 18 10:04:16 AM UTC 24 1092800006 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3305047860 Sep 18 10:04:16 AM UTC 24 Sep 18 10:04:28 AM UTC 24 3207463258 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1666681195 Sep 18 10:01:36 AM UTC 24 Sep 18 10:04:36 AM UTC 24 6350239944 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2959538334 Sep 18 10:01:34 AM UTC 24 Sep 18 10:04:40 AM UTC 24 14607739399 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3618016666 Sep 18 10:04:37 AM UTC 24 Sep 18 10:04:51 AM UTC 24 2682456411 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1226977796 Sep 18 10:03:08 AM UTC 24 Sep 18 10:04:54 AM UTC 24 24847290611 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.142339009 Sep 18 10:03:59 AM UTC 24 Sep 18 10:04:56 AM UTC 24 14402744290 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.867984223 Sep 18 10:04:32 AM UTC 24 Sep 18 10:05:10 AM UTC 24 14115288881 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2995872824 Sep 18 10:05:11 AM UTC 24 Sep 18 10:05:19 AM UTC 24 720015067 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2810803129 Sep 18 10:04:41 AM UTC 24 Sep 18 10:05:27 AM UTC 24 6287409927 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.2961158356 Sep 18 10:02:09 AM UTC 24 Sep 18 10:05:42 AM UTC 24 41324505051 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.4107626566 Sep 18 10:01:22 AM UTC 24 Sep 18 10:05:47 AM UTC 24 12310892757 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.1538547810 Sep 18 10:01:25 AM UTC 24 Sep 18 10:06:25 AM UTC 24 14229378195 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.570552214 Sep 18 10:06:26 AM UTC 24 Sep 18 10:06:30 AM UTC 24 208172801 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2639679580 Sep 18 10:06:32 AM UTC 24 Sep 18 10:06:34 AM UTC 24 12756903 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2785585986 Sep 18 10:03:35 AM UTC 24 Sep 18 10:06:41 AM UTC 24 7090801791 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3939030938 Sep 18 10:03:29 AM UTC 24 Sep 18 10:06:45 AM UTC 24 6917522030 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1113618010 Sep 18 10:05:42 AM UTC 24 Sep 18 10:06:46 AM UTC 24 2985044211 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3823002241 Sep 18 10:04:28 AM UTC 24 Sep 18 10:07:03 AM UTC 24 10573020148 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2695569602 Sep 18 10:02:06 AM UTC 24 Sep 18 10:07:24 AM UTC 24 6472803759 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1503208882 Sep 18 10:02:36 AM UTC 24 Sep 18 10:07:25 AM UTC 24 4279089343 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.111132742 Sep 18 10:07:03 AM UTC 24 Sep 18 10:07:37 AM UTC 24 1529426678 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.445463812 Sep 18 10:01:14 AM UTC 24 Sep 18 10:07:38 AM UTC 24 10651478837 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1509865840 Sep 18 10:07:26 AM UTC 24 Sep 18 10:07:43 AM UTC 24 2823900979 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1429708918 Sep 18 10:01:14 AM UTC 24 Sep 18 10:07:44 AM UTC 24 31065440256 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2469471390 Sep 18 10:01:46 AM UTC 24 Sep 18 10:07:50 AM UTC 24 46506842166 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.2489992157 Sep 18 10:01:31 AM UTC 24 Sep 18 10:07:50 AM UTC 24 45038315661 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1241451840 Sep 18 10:07:37 AM UTC 24 Sep 18 10:07:53 AM UTC 24 1392216717 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2743992749 Sep 18 10:07:51 AM UTC 24 Sep 18 10:07:56 AM UTC 24 410249999 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.24085956 Sep 18 10:06:35 AM UTC 24 Sep 18 10:08:00 AM UTC 24 1832845939 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.2653782894 Sep 18 10:05:27 AM UTC 24 Sep 18 10:08:34 AM UTC 24 9349234940 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2462678732 Sep 18 10:07:59 AM UTC 24 Sep 18 10:08:36 AM UTC 24 872453889 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3003458321 Sep 18 10:08:35 AM UTC 24 Sep 18 10:08:37 AM UTC 24 13156138 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.836581789 Sep 18 10:02:06 AM UTC 24 Sep 18 10:08:39 AM UTC 24 9642433817 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3608184143 Sep 18 10:02:38 AM UTC 24 Sep 18 10:08:41 AM UTC 24 25019253004 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3077637107 Sep 18 10:07:39 AM UTC 24 Sep 18 10:08:58 AM UTC 24 10398892892 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1108244619 Sep 18 10:08:36 AM UTC 24 Sep 18 10:08:59 AM UTC 24 1988235906 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.2382255851 Sep 18 10:08:59 AM UTC 24 Sep 18 10:09:08 AM UTC 24 1197670043 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3687040293 Sep 18 10:09:09 AM UTC 24 Sep 18 10:09:38 AM UTC 24 8783727518 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3326996906 Sep 18 10:04:52 AM UTC 24 Sep 18 10:09:46 AM UTC 24 24901646809 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.20188681 Sep 18 10:04:09 AM UTC 24 Sep 18 10:09:52 AM UTC 24 7257037427 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2501197079 Sep 18 10:01:16 AM UTC 24 Sep 18 10:09:55 AM UTC 24 7695145461 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.123925698 Sep 18 10:02:43 AM UTC 24 Sep 18 10:10:06 AM UTC 24 147898492534 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.4124054963 Sep 18 10:01:44 AM UTC 24 Sep 18 10:10:07 AM UTC 24 14756148700 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1745822202 Sep 18 10:10:08 AM UTC 24 Sep 18 10:10:13 AM UTC 24 680817476 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.87580095 Sep 18 10:02:03 AM UTC 24 Sep 18 10:10:21 AM UTC 24 43004553452 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2116492930 Sep 18 10:04:01 AM UTC 24 Sep 18 10:10:22 AM UTC 24 3839915390 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1687815898 Sep 18 10:06:47 AM UTC 24 Sep 18 10:10:24 AM UTC 24 22950796330 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2892772355 Sep 18 10:09:47 AM UTC 24 Sep 18 10:10:26 AM UTC 24 8354470849 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3262281914 Sep 18 10:10:27 AM UTC 24 Sep 18 10:10:29 AM UTC 24 15235914 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1897258032 Sep 18 10:07:57 AM UTC 24 Sep 18 10:10:34 AM UTC 24 19945502377 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3364104176 Sep 18 10:01:22 AM UTC 24 Sep 18 10:10:38 AM UTC 24 9459981438 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.1477313854 Sep 18 10:10:30 AM UTC 24 Sep 18 10:10:57 AM UTC 24 2071265152 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.247534190 Sep 18 10:07:54 AM UTC 24 Sep 18 10:11:10 AM UTC 24 41336426530 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.204476976 Sep 18 10:10:23 AM UTC 24 Sep 18 10:11:16 AM UTC 24 3846017366 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.446860310 Sep 18 10:09:39 AM UTC 24 Sep 18 10:11:23 AM UTC 24 7772993035 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.414100732 Sep 18 10:04:54 AM UTC 24 Sep 18 10:11:26 AM UTC 24 27201433611 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.293660304 Sep 18 10:10:58 AM UTC 24 Sep 18 10:11:29 AM UTC 24 5165308620 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2903694069 Sep 18 10:01:15 AM UTC 24 Sep 18 10:11:38 AM UTC 24 15948256305 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1389181150 Sep 18 10:10:22 AM UTC 24 Sep 18 10:11:46 AM UTC 24 1956381115 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.175348592 Sep 18 10:05:19 AM UTC 24 Sep 18 10:11:46 AM UTC 24 71752755238 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3597347289 Sep 18 10:11:47 AM UTC 24 Sep 18 10:11:54 AM UTC 24 743317878 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.1945504025 Sep 18 10:01:15 AM UTC 24 Sep 18 10:11:59 AM UTC 24 20861109102 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3047073835 Sep 18 10:11:25 AM UTC 24 Sep 18 10:12:01 AM UTC 24 781869143 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1324084615 Sep 18 10:11:17 AM UTC 24 Sep 18 10:12:10 AM UTC 24 3027328625 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1543868598 Sep 18 10:12:02 AM UTC 24 Sep 18 10:12:15 AM UTC 24 802268015 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2640786318 Sep 18 10:12:16 AM UTC 24 Sep 18 10:12:19 AM UTC 24 13524105 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3186750929 Sep 18 10:11:27 AM UTC 24 Sep 18 10:12:22 AM UTC 24 15703228738 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1671093107 Sep 18 10:12:20 AM UTC 24 Sep 18 10:12:32 AM UTC 24 1753584263 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2353985028 Sep 18 10:01:48 AM UTC 24 Sep 18 10:12:38 AM UTC 24 24060484475 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.4013136983 Sep 18 10:07:25 AM UTC 24 Sep 18 10:13:26 AM UTC 24 20514695497 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4165862969 Sep 18 10:03:21 AM UTC 24 Sep 18 10:13:41 AM UTC 24 11911586801 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.2403202780 Sep 18 10:03:14 AM UTC 24 Sep 18 10:13:59 AM UTC 24 34431958650 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2504370697 Sep 18 10:10:32 AM UTC 24 Sep 18 10:14:06 AM UTC 24 34140503707 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2360023954 Sep 18 10:11:54 AM UTC 24 Sep 18 10:14:09 AM UTC 24 2744869267 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2579567017 Sep 18 10:10:14 AM UTC 24 Sep 18 10:14:09 AM UTC 24 8208989180 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3153216945 Sep 18 10:13:27 AM UTC 24 Sep 18 10:14:22 AM UTC 24 2779473980 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1616653351 Sep 18 10:10:38 AM UTC 24 Sep 18 10:14:34 AM UTC 24 3126547365 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3834879972 Sep 18 10:14:35 AM UTC 24 Sep 18 10:14:41 AM UTC 24 1410539805 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1373015288 Sep 18 10:14:06 AM UTC 24 Sep 18 10:15:01 AM UTC 24 16613590606 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3918024223 Sep 18 10:13:59 AM UTC 24 Sep 18 10:15:04 AM UTC 24 785003358 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3054823043 Sep 18 10:13:57 AM UTC 24 Sep 18 10:15:07 AM UTC 24 1473532101 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2266841927 Sep 18 10:12:00 AM UTC 24 Sep 18 10:15:23 AM UTC 24 5578299918 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4098408853 Sep 18 10:15:23 AM UTC 24 Sep 18 10:15:26 AM UTC 24 41689726 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2112627468 Sep 18 10:15:04 AM UTC 24 Sep 18 10:15:27 AM UTC 24 456924620 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.3054361116 Sep 18 10:15:26 AM UTC 24 Sep 18 10:15:40 AM UTC 24 1472793269 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2651424341 Sep 18 10:08:42 AM UTC 24 Sep 18 10:15:54 AM UTC 24 25157065295 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.357577351 Sep 18 10:01:31 AM UTC 24 Sep 18 10:16:10 AM UTC 24 25191255022 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.1989095462 Sep 18 10:08:38 AM UTC 24 Sep 18 10:16:11 AM UTC 24 10737668114 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1775439048 Sep 18 10:16:12 AM UTC 24 Sep 18 10:16:25 AM UTC 24 1651411207 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.569003223 Sep 18 10:03:10 AM UTC 24 Sep 18 10:16:59 AM UTC 24 28283711296 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3679061756 Sep 18 10:14:42 AM UTC 24 Sep 18 10:17:03 AM UTC 24 5977466366 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1769841796 Sep 18 10:16:59 AM UTC 24 Sep 18 10:17:14 AM UTC 24 11103812652 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.604729387 Sep 18 10:12:39 AM UTC 24 Sep 18 10:17:58 AM UTC 24 10316517276 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2483545560 Sep 18 10:16:26 AM UTC 24 Sep 18 10:18:05 AM UTC 24 2953928794 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2693725587 Sep 18 10:15:02 AM UTC 24 Sep 18 10:18:18 AM UTC 24 6373354894 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2288252785 Sep 18 10:17:04 AM UTC 24 Sep 18 10:18:23 AM UTC 24 25992285997 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3181318582 Sep 18 10:18:19 AM UTC 24 Sep 18 10:18:27 AM UTC 24 1408578332 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2288843277 Sep 18 10:09:01 AM UTC 24 Sep 18 10:18:53 AM UTC 24 47555171163 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1845718697 Sep 18 10:18:54 AM UTC 24 Sep 18 10:19:27 AM UTC 24 3285763056 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3391123389 Sep 18 10:15:55 AM UTC 24 Sep 18 10:19:27 AM UTC 24 10609144570 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.138432928 Sep 18 10:19:28 AM UTC 24 Sep 18 10:19:29 AM UTC 24 34773136 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3498890267 Sep 18 10:11:11 AM UTC 24 Sep 18 10:19:33 AM UTC 24 25309643191 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3678086660 Sep 18 10:11:30 AM UTC 24 Sep 18 10:19:47 AM UTC 24 53418153566 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1865467282 Sep 18 10:19:31 AM UTC 24 Sep 18 10:20:05 AM UTC 24 1869872994 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.265324548 Sep 18 10:14:23 AM UTC 24 Sep 18 10:20:37 AM UTC 24 11663053875 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.758142093 Sep 18 10:18:27 AM UTC 24 Sep 18 10:20:51 AM UTC 24 19003303019 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3936148294 Sep 18 10:18:24 AM UTC 24 Sep 18 10:21:11 AM UTC 24 10516593985 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1627961330 Sep 18 10:20:38 AM UTC 24 Sep 18 10:21:51 AM UTC 24 2197385469 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.1704149629 Sep 18 10:01:46 AM UTC 24 Sep 18 10:22:04 AM UTC 24 55506231928 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.4012987873 Sep 18 10:21:11 AM UTC 24 Sep 18 10:22:10 AM UTC 24 3118413843 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.233744089 Sep 18 10:01:13 AM UTC 24 Sep 18 10:22:15 AM UTC 24 120077071543 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.1564577777 Sep 18 10:20:51 AM UTC 24 Sep 18 10:22:15 AM UTC 24 4776963950 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.496545056 Sep 18 10:10:34 AM UTC 24 Sep 18 10:22:21 AM UTC 24 93118897309 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1958286100 Sep 18 10:16:12 AM UTC 24 Sep 18 10:22:22 AM UTC 24 50464189901 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3012392100 Sep 18 10:22:16 AM UTC 24 Sep 18 10:22:23 AM UTC 24 697741633 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.1328609031 Sep 18 10:04:01 AM UTC 24 Sep 18 10:22:27 AM UTC 24 110736258453 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3794390618 Sep 18 10:07:45 AM UTC 24 Sep 18 10:22:38 AM UTC 24 70899233789 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1521899025 Sep 18 10:22:40 AM UTC 24 Sep 18 10:22:41 AM UTC 24 23381318 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1888771088 Sep 18 10:04:56 AM UTC 24 Sep 18 10:22:49 AM UTC 24 5492373903 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.1849593592 Sep 18 10:07:44 AM UTC 24 Sep 18 10:22:52 AM UTC 24 15690189131 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.855882927 Sep 18 10:06:46 AM UTC 24 Sep 18 10:22:57 AM UTC 24 166423118593 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.302439909 Sep 18 10:14:10 AM UTC 24 Sep 18 10:23:01 AM UTC 24 25881852878 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.127893119 Sep 18 10:22:23 AM UTC 24 Sep 18 10:23:04 AM UTC 24 3623660266 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2039250825 Sep 18 10:22:43 AM UTC 24 Sep 18 10:23:07 AM UTC 24 10665257602 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.1233669355 Sep 18 10:09:52 AM UTC 24 Sep 18 10:23:07 AM UTC 24 14251751437 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4283116191 Sep 18 10:23:02 AM UTC 24 Sep 18 10:23:34 AM UTC 24 3654448132 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.376717517 Sep 18 10:23:08 AM UTC 24 Sep 18 10:23:45 AM UTC 24 2881951919 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3219062832 Sep 18 10:23:34 AM UTC 24 Sep 18 10:23:48 AM UTC 24 13585301330 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.1305905724 Sep 18 10:21:52 AM UTC 24 Sep 18 10:23:50 AM UTC 24 60510553564 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.65651748 Sep 18 10:13:42 AM UTC 24 Sep 18 10:24:06 AM UTC 24 20946214228 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3411479847 Sep 18 10:24:08 AM UTC 24 Sep 18 10:24:15 AM UTC 24 746554731 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2351705399 Sep 18 10:23:08 AM UTC 24 Sep 18 10:24:25 AM UTC 24 3267470461 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.1856296537 Sep 18 10:11:47 AM UTC 24 Sep 18 10:24:42 AM UTC 24 9037011382 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2852870832 Sep 18 10:18:06 AM UTC 24 Sep 18 10:24:44 AM UTC 24 47817403677 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3598453820 Sep 18 10:06:43 AM UTC 24 Sep 18 10:25:28 AM UTC 24 296972733909 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1252287452 Sep 18 10:25:28 AM UTC 24 Sep 18 10:25:30 AM UTC 24 19291522 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.464509282 Sep 18 10:22:23 AM UTC 24 Sep 18 10:25:33 AM UTC 24 4398242340 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2456271073 Sep 18 10:17:15 AM UTC 24 Sep 18 10:25:36 AM UTC 24 15139308983 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.1476348707 Sep 18 10:25:31 AM UTC 24 Sep 18 10:25:40 AM UTC 24 348229491 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.715464209 Sep 18 10:22:21 AM UTC 24 Sep 18 10:26:01 AM UTC 24 18319544209 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2526797044 Sep 18 10:23:50 AM UTC 24 Sep 18 10:26:03 AM UTC 24 19076336805 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3653941998 Sep 18 10:24:26 AM UTC 24 Sep 18 10:26:07 AM UTC 24 10892339306 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.73572892 Sep 18 10:26:02 AM UTC 24 Sep 18 10:26:32 AM UTC 24 1378590542 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.817755998 Sep 18 10:20:06 AM UTC 24 Sep 18 10:26:35 AM UTC 24 5711169401 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.719734161 Sep 18 10:26:08 AM UTC 24 Sep 18 10:26:40 AM UTC 24 741618729 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2011053830 Sep 18 10:22:58 AM UTC 24 Sep 18 10:26:40 AM UTC 24 2168208904 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2688429121 Sep 18 10:24:16 AM UTC 24 Sep 18 10:27:02 AM UTC 24 32877263798 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3548139587 Sep 18 10:26:33 AM UTC 24 Sep 18 10:27:15 AM UTC 24 3922259288 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4098030956 Sep 18 10:20:45 AM UTC 24 Sep 18 10:27:18 AM UTC 24 16466599555 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.1057050948 Sep 18 10:23:51 AM UTC 24 Sep 18 10:27:18 AM UTC 24 33310492917 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.284185738 Sep 18 10:27:17 AM UTC 24 Sep 18 10:27:22 AM UTC 24 1412898746 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3550755321 Sep 18 10:27:23 AM UTC 24 Sep 18 10:27:47 AM UTC 24 533706443 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1846011333 Sep 18 10:24:43 AM UTC 24 Sep 18 10:27:49 AM UTC 24 2666559349 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.4025714795 Sep 18 10:27:50 AM UTC 24 Sep 18 10:27:52 AM UTC 24 13889286 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3790374645 Sep 18 10:26:35 AM UTC 24 Sep 18 10:27:56 AM UTC 24 9213470099 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1980632789 Sep 18 10:27:53 AM UTC 24 Sep 18 10:28:01 AM UTC 24 1582392047 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1162602891 Sep 18 10:10:06 AM UTC 24 Sep 18 10:28:28 AM UTC 24 8326296006 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.649386206 Sep 18 10:27:19 AM UTC 24 Sep 18 10:28:52 AM UTC 24 3030143357 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.428033804 Sep 18 10:07:51 AM UTC 24 Sep 18 10:29:05 AM UTC 24 59196447965 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.659882614 Sep 18 10:28:52 AM UTC 24 Sep 18 10:29:17 AM UTC 24 1087935355 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.681303623 Sep 18 10:11:39 AM UTC 24 Sep 18 10:29:39 AM UTC 24 29656884988 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.669086800 Sep 18 10:29:18 AM UTC 24 Sep 18 10:29:44 AM UTC 24 9846680037 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1562743711 Sep 18 10:09:55 AM UTC 24 Sep 18 10:29:48 AM UTC 24 8397796073 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1015110687 Sep 18 10:22:11 AM UTC 24 Sep 18 10:29:50 AM UTC 24 21305187462 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.613627019 Sep 18 10:22:05 AM UTC 24 Sep 18 10:29:53 AM UTC 24 34151898406 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1164868015 Sep 18 10:27:19 AM UTC 24 Sep 18 10:30:03 AM UTC 24 1979897316 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3638720803 Sep 18 10:30:03 AM UTC 24 Sep 18 10:30:10 AM UTC 24 446189881 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1857302553 Sep 18 10:29:40 AM UTC 24 Sep 18 10:31:21 AM UTC 24 820978715 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.4016016694 Sep 18 10:29:45 AM UTC 24 Sep 18 10:31:22 AM UTC 24 50433343620 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3567702280 Sep 18 10:15:27 AM UTC 24 Sep 18 10:31:25 AM UTC 24 62983780585 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3008005100 Sep 18 10:22:50 AM UTC 24 Sep 18 10:31:27 AM UTC 24 8175639213 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1575069932 Sep 18 10:31:28 AM UTC 24 Sep 18 10:31:30 AM UTC 24 12084620 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2705847342 Sep 18 10:31:23 AM UTC 24 Sep 18 10:31:40 AM UTC 24 1271104004 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.539643204 Sep 18 10:25:41 AM UTC 24 Sep 18 10:31:59 AM UTC 24 57389789581 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2473024637 Sep 18 10:26:04 AM UTC 24 Sep 18 10:32:02 AM UTC 24 5564519817 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2808253439 Sep 18 10:25:33 AM UTC 24 Sep 18 10:32:08 AM UTC 24 15670650496 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.3609641833 Sep 18 10:31:31 AM UTC 24 Sep 18 10:32:21 AM UTC 24 1126212187 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3265700162 Sep 18 10:32:29 AM UTC 24 Sep 18 10:32:40 AM UTC 24 717511197 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2890120539 Sep 18 10:31:23 AM UTC 24 Sep 18 10:33:05 AM UTC 24 5322259362 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.716661122 Sep 18 10:27:02 AM UTC 24 Sep 18 10:33:24 AM UTC 24 16705754286 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3047391052 Sep 18 10:30:11 AM UTC 24 Sep 18 10:33:53 AM UTC 24 7209519560 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1010313240 Sep 18 10:32:09 AM UTC 24 Sep 18 10:34:01 AM UTC 24 539128096 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.601196559 Sep 18 10:19:34 AM UTC 24 Sep 18 10:34:13 AM UTC 24 277375971062 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3227968055 Sep 18 10:34:13 AM UTC 24 Sep 18 10:34:22 AM UTC 24 1777828472 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.3607726437 Sep 18 10:08:40 AM UTC 24 Sep 18 10:34:26 AM UTC 24 102619752591 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2645840928 Sep 18 10:32:41 AM UTC 24 Sep 18 10:34:31 AM UTC 24 3125908800 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.742070171 Sep 18 10:33:06 AM UTC 24 Sep 18 10:35:08 AM UTC 24 12306538340 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.4160032060 Sep 18 10:28:28 AM UTC 24 Sep 18 10:35:20 AM UTC 24 22353417838 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.3065205553 Sep 18 10:35:20 AM UTC 24 Sep 18 10:35:22 AM UTC 24 12443685 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.117771455 Sep 18 10:17:59 AM UTC 24 Sep 18 10:35:28 AM UTC 24 88070124099 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3857901645 Sep 18 10:34:32 AM UTC 24 Sep 18 10:35:41 AM UTC 24 3627518443 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3918865914 Sep 18 10:14:10 AM UTC 24 Sep 18 10:35:46 AM UTC 24 107086731010 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.654857029 Sep 18 10:27:57 AM UTC 24 Sep 18 10:35:50 AM UTC 24 21071574125 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.402580719 Sep 18 10:35:23 AM UTC 24 Sep 18 10:35:54 AM UTC 24 400048232 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.621376958 Sep 18 10:35:51 AM UTC 24 Sep 18 10:36:14 AM UTC 24 1937409365 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.4118841698 Sep 18 10:28:02 AM UTC 24 Sep 18 10:36:16 AM UTC 24 27600145320 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.308302743 Sep 18 10:23:45 AM UTC 24 Sep 18 10:36:19 AM UTC 24 10459713518 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.4017472463 Sep 18 10:36:15 AM UTC 24 Sep 18 10:36:29 AM UTC 24 2688116541 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.3932552667 Sep 18 10:26:41 AM UTC 24 Sep 18 10:36:35 AM UTC 24 7813959699 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3036007821 Sep 18 10:36:17 AM UTC 24 Sep 18 10:36:48 AM UTC 24 2977890399 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.2444133857 Sep 18 10:01:13 AM UTC 24 Sep 18 10:37:04 AM UTC 24 102689964735 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1468809374 Sep 18 10:37:05 AM UTC 24 Sep 18 10:37:11 AM UTC 24 574464411 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.3768738854 Sep 18 10:34:22 AM UTC 24 Sep 18 10:37:13 AM UTC 24 8223597220 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3362318327 Sep 18 10:29:06 AM UTC 24 Sep 18 10:37:32 AM UTC 24 6680656143 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3542459856 Sep 18 10:36:20 AM UTC 24 Sep 18 10:37:36 AM UTC 24 41542486418 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.278802305 Sep 18 10:12:23 AM UTC 24 Sep 18 10:37:49 AM UTC 24 47174877386 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2252721448 Sep 18 10:37:50 AM UTC 24 Sep 18 10:37:52 AM UTC 24 14127065 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2487328780 Sep 18 10:34:26 AM UTC 24 Sep 18 10:38:05 AM UTC 24 5458356229 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.4069171950 Sep 18 10:34:01 AM UTC 24 Sep 18 10:38:16 AM UTC 24 5231601392 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.1270547323 Sep 18 10:37:53 AM UTC 24 Sep 18 10:38:18 AM UTC 24 2664574947 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.1293035933 Sep 18 10:33:54 AM UTC 24 Sep 18 10:38:36 AM UTC 24 33137616960 ps