Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16395269

1

T2

54

T4

57

T5

454

full_word

156990093

1

T2

465

T4

649

T5

2011

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	173385042	1			T2	519		T4	706		T5	2465
auto[TlIntgErrCmd]	124	1			T115	5		T116	5		T117	3
auto[TlIntgErrData]	92	1			T115	3		T116	3		T117	3
auto[TlIntgErrBoth]	104	1			T115	2		T116	2		T117	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83511881

1

T2

268

T4

332

T5

1278

auto[1]

89873481

1

T2

251

T4

374

T5

1187

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8031907	1			T2	27		T4	22		T5	231
auto[TlIntgErrNone]	partial	auto[1]	8363068	1			T2	27		T4	35		T5	223
auto[TlIntgErrNone]	full_word	auto[0]	75479822	1			T2	241		T4	310		T5	1047
auto[TlIntgErrNone]	full_word	auto[1]	81510245	1			T2	224		T4	339		T5	964
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T115	3		T116	1		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T115	2		T116	4		T117	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T130	1		T137	1		T135	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T133	1		T130	1		T135	2
auto[TlIntgErrData]	partial	auto[0]	42	1			T115	2		T116	3		T117	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T115	1		T117	2		T128	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T129	2		T130	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T131	1		T138	1		T139	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T115	1		T116	1		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T115	1		T116	1		T117	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T139	1		T140	1		T141	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T138	1		T141	1		-	-