Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	944417	1			T8	1		T34	1		T9	6
auto[1]	11153905	1			T5	1278		T8	1		T12	195
auto[2]	731550	1			T34	3		T9	5		T35	404
auto[3]	10887737	1			T5	1186		T8	1		T12	154

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14776407	1			T5	1619		T12	349		T29	8617
auto[1]	2239600	1			T5	391		T22	227		T30	326
auto[2]	2288214	1			T5	378		T8	1		T22	264
auto[3]	4413388	1			T5	76		T8	2		T22	44

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9488274

1

T5

2464

T8

3

T12

349

auto[1]

14229335

1

T21

1

T36

1

T49

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	462212	1			T9	3		T35	553		T37	4
auto[0]	auto[0]	auto[1]	47559	1			T9	1		T35	47		T37	10
auto[0]	auto[0]	auto[2]	47305	1			T8	1		T9	1		T35	55
auto[0]	auto[0]	auto[3]	56994	1			T34	1		T9	1		T35	2
auto[0]	auto[1]	auto[0]	3229161	1			T5	839		T12	195		T29	4207
auto[0]	auto[1]	auto[1]	351421	1			T5	208		T22	100		T30	149
auto[0]	auto[1]	auto[2]	354302	1			T5	195		T22	137		T30	153
auto[0]	auto[1]	auto[3]	380120	1			T5	36		T8	1		T22	19
auto[0]	auto[2]	auto[0]	339386	1			T9	4		T35	308		T48	112
auto[0]	auto[2]	auto[1]	37538	1			T9	1		T35	32		T48	13
auto[0]	auto[2]	auto[2]	39058	1			T35	59		T37	7		T48	24
auto[0]	auto[2]	auto[3]	40639	1			T34	3		T35	5		T37	20
auto[0]	auto[3]	auto[0]	3062161	1			T5	780		T12	154		T29	4410
auto[0]	auto[3]	auto[1]	333163	1			T5	183		T22	127		T30	177
auto[0]	auto[3]	auto[2]	362473	1			T5	183		T22	127		T30	177
auto[0]	auto[3]	auto[3]	344782	1			T5	40		T8	1		T22	25
auto[1]	auto[0]	auto[0]	10739	1			T59	220		T106	492		T110	126
auto[1]	auto[0]	auto[1]	48956	1			T59	975		T106	2179		T110	585
auto[1]	auto[0]	auto[2]	48984	1			T59	972		T106	2115		T110	535
auto[1]	auto[0]	auto[3]	221668	1			T59	4337		T106	9970		T110	2464
auto[1]	auto[1]	auto[0]	3833026	1			T59	145		T60	61435		T106	66
auto[1]	auto[1]	auto[1]	702735	1			T59	1158		T60	6026		T106	2210
auto[1]	auto[1]	auto[2]	698104	1			T59	604		T60	6058		T106	354
auto[1]	auto[1]	auto[3]	1605036	1			T59	5172		T60	646		T106	10061
auto[1]	auto[2]	auto[0]	7508	1			T59	121		T106	448		T151	234
auto[1]	auto[2]	auto[1]	34398	1			T59	570		T106	2046		T151	1057
auto[1]	auto[2]	auto[2]	42305	1			T59	1106		T106	1891		T110	510
auto[1]	auto[2]	auto[3]	190718	1			T59	4762		T106	8337		T110	2162
auto[1]	auto[3]	auto[0]	3832214	1			T21	1		T59	68		T60	61267
auto[1]	auto[3]	auto[1]	683830	1			T36	1		T59	244		T60	6093
auto[1]	auto[3]	auto[2]	695683	1			T49	1		T78	1		T59	1270
auto[1]	auto[3]	auto[3]	1573431	1			T59	5658		T60	632		T106	8597