Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1226927383	216188	0	0
ctrl_regwen_rd_A	1226927383	3445	0	0
exec_rd_A	1226927383	3125	0	0
exec_regwen_rd_A	1226927383	3461	0	0
readback_rd_A	1226927383	5289	0	0
readback_regwen_rd_A	1226927383	2177	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226927383	216188	0	0
T10	128563	0	0	0
T23	87372	6031	0	0
T24	181666	5358	0	0
T25	0	9143	0	0
T28	220491	0	0	0
T38	0	5453	0	0
T42	307094	0	0	0
T48	92651	0	0	0
T49	76466	0	0	0
T50	34242	0	0	0
T51	94103	0	0	0
T52	73245	0	0	0
T61	0	1852	0	0
T62	0	1151	0	0
T63	0	1782	0	0
T64	0	1618	0	0
T65	0	3025	0	0
T66	0	758	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226927383	3445	0	0
T10	128563	0	0	0
T24	181666	450	0	0
T32	20516	0	0	0
T38	0	250	0	0
T49	76466	0	0	0
T50	34242	0	0	0
T51	94103	0	0	0
T52	73245	0	0	0
T57	314305	0	0	0
T58	1080	0	0	0
T66	0	125	0	0
T118	0	28	0	0
T119	0	341	0	0
T120	0	556	0	0
T121	0	87	0	0
T122	0	262	0	0
T123	0	228	0	0
T124	0	45	0	0
T125	74957	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226927383	3125	0	0
T10	128563	0	0	0
T24	181666	337	0	0
T32	20516	0	0	0
T38	0	213	0	0
T49	76466	0	0	0
T50	34242	0	0	0
T51	94103	0	0	0
T52	73245	0	0	0
T57	314305	0	0	0
T58	1080	0	0	0
T66	0	85	0	0
T118	0	63	0	0
T119	0	384	0	0
T120	0	367	0	0
T121	0	80	0	0
T122	0	253	0	0
T123	0	182	0	0
T124	0	42	0	0
T125	74957	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226927383	3461	0	0
T10	128563	0	0	0
T24	181666	372	0	0
T32	20516	0	0	0
T38	0	193	0	0
T49	76466	0	0	0
T50	34242	0	0	0
T51	94103	0	0	0
T52	73245	0	0	0
T57	314305	0	0	0
T58	1080	0	0	0
T66	0	62	0	0
T118	0	30	0	0
T119	0	511	0	0
T120	0	552	0	0
T121	0	68	0	0
T122	0	296	0	0
T123	0	221	0	0
T124	0	80	0	0
T125	74957	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226927383	5289	0	0
T10	128563	0	0	0
T16	0	101	0	0
T24	181666	280	0	0
T28	220491	11	0	0
T32	20516	0	0	0
T38	0	193	0	0
T49	76466	0	0	0
T50	34242	0	0	0
T51	94103	0	0	0
T52	73245	0	0	0
T57	314305	0	0	0
T58	1080	0	0	0
T66	0	99	0	0
T113	0	75	0	0
T114	0	141	0	0
T118	0	19	0	0
T126	0	158	0	0
T127	0	55	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226927383	2177	0	0
T10	128563	0	0	0
T24	181666	369	0	0
T32	20516	0	0	0
T38	0	218	0	0
T49	76466	0	0	0
T50	34242	0	0	0
T51	94103	0	0	0
T52	73245	0	0	0
T57	314305	0	0	0
T58	1080	0	0	0
T66	0	72	0	0
T118	0	18	0	0
T119	0	294	0	0
T120	0	408	0	0
T121	0	21	0	0
T122	0	215	0	0
T123	0	179	0	0
T124	0	81	0	0
T125	74957	0	0	0