Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	349106066	1			T2	20096		T3	90846		T4	1120
instr_valid_dis	296416668	1			T2	20096		T3	66360		T4	1120
instr_en	40311005	1			T3	24486		T23	54		T24	53540

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12495580	1			T3	34128		T23	14720		T24	31680
sram_ifetch_valid_disable	307882220	1			T2	20096		T3	44330		T4	1120
sram_ifetch_enable	28728266	1			T3	12388		T23	79978		T24	67058

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	349106066	1			T2	20096		T3	90846		T4	1120
hw_debug_en_valid_off	304595505	1			T2	20096		T3	59528		T4	1120
hw_debug_en_on	30040719	1			T3	27738		T23	107578		T24	89496

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	307882220	1			T2	20096		T3	44330		T4	1120
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	283825914	1			T2	20096		T3	19844		T4	1120
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	17785253	1			T3	24486		T112	24762		T146	17482
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5502006	1			T3	34128		T24	15720		T112	44946
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1715962	1			T3	34128		T146	63294		T147	58
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3333270	1			T112	44946		T159	19878		T160	16314
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4842240	1			T23	14720		T147	52302		T38	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1620880	1			T23	14666		T147	13104		T154	21910
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2579266	1			T23	54		T147	21618		T38	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	14806449	1			T3	19844		T23	39146		T24	51916
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	6290604	1			T3	19844		T23	39146		T146	14120
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4350213	1			T146	17482		T149	21716		T154	27492

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	15806260	1			T24	37580		T112	11092		T146	25276
lc_exec_en	10392030	1			T3	7894		T23	53712		T24	37580
valid_exec_dis	292743535	1			T2	20096		T3	36874		T4	1120
invalid_exec_dis	41223846	1			T3	46516		T23	94698		T24	98738