Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.30 99.25 95.11 99.72 100.00 96.38 99.13 98.54


Total tests in report: 1035
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
73.05 73.05 91.95 91.95 78.32 78.32 92.36 92.36 23.81 23.81 82.84 82.84 93.47 93.47 48.63 48.63 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.32174703
85.04 11.99 96.81 4.86 81.64 3.32 92.36 0.00 90.48 66.67 90.44 7.60 94.92 1.45 48.63 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.627004288
91.33 6.30 97.40 0.59 86.26 4.62 96.69 4.34 90.48 0.00 91.67 1.23 96.23 1.31 80.62 31.99 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1420419965
94.25 2.92 98.74 1.34 89.45 3.20 98.04 1.34 100.00 9.52 94.85 3.19 96.95 0.73 81.72 1.10 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1216247842
95.07 0.82 98.74 0.00 90.05 0.59 98.04 0.00 100.00 0.00 94.85 0.00 96.95 0.00 86.84 5.12 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1697979153
95.77 0.70 98.91 0.17 91.35 1.30 98.31 0.28 100.00 0.00 95.83 0.98 96.95 0.00 89.03 2.19 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1274439327
96.36 0.59 99.16 0.25 91.35 0.00 98.31 0.00 100.00 0.00 96.08 0.25 97.10 0.15 92.50 3.47 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.982530560
96.67 0.31 99.16 0.00 91.35 0.00 98.31 0.00 100.00 0.00 96.08 0.00 97.10 0.00 94.70 2.19 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.639316131
96.87 0.20 99.16 0.00 91.47 0.12 98.31 0.00 100.00 0.00 96.57 0.49 97.68 0.58 94.88 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2048471353
97.04 0.18 99.16 0.00 91.47 0.00 98.38 0.07 100.00 0.00 96.57 0.00 98.84 1.16 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1847484722
97.20 0.15 99.16 0.00 91.47 0.00 98.59 0.21 100.00 0.00 96.57 0.00 98.98 0.15 95.61 0.73 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.3081123946
97.33 0.13 99.25 0.08 91.47 0.00 99.41 0.83 100.00 0.00 96.57 0.00 98.98 0.00 95.61 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4062309626
97.43 0.10 99.25 0.00 91.47 0.00 99.41 0.00 100.00 0.00 96.57 0.00 98.98 0.00 96.34 0.73 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2399608494
97.54 0.10 99.25 0.00 91.47 0.00 99.41 0.00 100.00 0.00 96.57 0.00 98.98 0.00 97.07 0.73 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3398164615
97.62 0.09 99.25 0.00 91.47 0.00 99.48 0.07 100.00 0.00 96.57 0.00 98.98 0.00 97.62 0.55 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.4035407622
97.70 0.07 99.25 0.00 91.82 0.36 99.62 0.14 100.00 0.00 96.57 0.00 98.98 0.00 97.62 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1400269205
97.75 0.05 99.25 0.00 91.82 0.00 99.62 0.00 100.00 0.00 96.57 0.00 98.98 0.00 97.99 0.37 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2866102300
97.79 0.04 99.25 0.00 91.82 0.00 99.72 0.10 100.00 0.00 96.57 0.00 98.98 0.00 98.17 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3890285459
97.81 0.03 99.25 0.00 91.82 0.00 99.72 0.00 100.00 0.00 96.57 0.00 98.98 0.00 98.35 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4196173286
97.84 0.03 99.25 0.00 91.82 0.00 99.72 0.00 100.00 0.00 96.57 0.00 98.98 0.00 98.54 0.18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.3194193510
97.86 0.02 99.25 0.00 91.82 0.00 99.72 0.00 100.00 0.00 96.57 0.00 99.13 0.15 98.54 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3983213671

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2488085994
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4049712122
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2004696410
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1269522277
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1722043626
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1006951017
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1103495017
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.99346315
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.612418180
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1151067519
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.212218727
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3862905283
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3990721162
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2722767548
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.98681754
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3388251509
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1971764261
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.405197783
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4135373016
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1287562527
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2056839409
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4083712058
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.289159245
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1797852802
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.847285500
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2250082074
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1578379614
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4289539953
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3493135872
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2862177497
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.488943314
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.684158370
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1071594621
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2466680680
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1079403259
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1308792241
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2884329723
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3491851891
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1251595406
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2832499899
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3255450729
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1724950723
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2942922741
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3139450468
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3228485859
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4201398740
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1242611727
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3416304753
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3782571438
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.301921113
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.368953299
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1744568330
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3700376026
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2111894440
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4072856189
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1286844724
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1565814254
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2512501898
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1111378378
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3197485303
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.702682714
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.441657143
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.425318493
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.142106018
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.69870410
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.289978509
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1618288661
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.653100225
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2015547686
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2553521777
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.687213457
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.4255365812
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2812096768
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3266496801
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2031675686
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1277874926
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3023635282
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3261696299
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1455387086
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1888152922
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.970660181
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1856159583
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.163924749
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2858232517
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1555066900
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.878482322
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.185145772
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.845790704
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.234031204
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/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3256075313
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2617389790
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.2330016662
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.992260733
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.622946168
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/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1336895993
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3951742187
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.990531146
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1607632494
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.701231988
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1909283439
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2573133218
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4267460272
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2995625633
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3430772780
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1912232238
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.3849308142
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.245270595
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.4246039933
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1916955393
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2476490092
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.842015215
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.77276221
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.137694048
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3552335395
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2467546510
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.2779809793
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.866546056
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1020910216
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.359860317
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.152535080
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.4213377023
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3638516617
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2620149304
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1157061040
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.2328925842
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.2676443271
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2198573630
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.389109002
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.926118862
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.911657215
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.4261827742
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.69383795
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2581712119
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3213197191
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2982219143
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2054740825
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2459760975
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1484461078
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2695603315
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1755338659
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2360659410
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1562411718
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2918757306
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.268508674
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.890105501
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1569204722
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1662047338
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3619337008
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.232694942
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3605862855
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.4167885882
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.952948338
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1591597905
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3387884612
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2137029295
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1251184595



Total test records in report: 1035
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.501063473 Oct 02 11:18:44 PM UTC 24 Oct 02 11:19:03 PM UTC 24 56069442 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.718075837 Oct 02 11:18:43 PM UTC 24 Oct 02 11:19:04 PM UTC 24 1401565916 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.32174703 Oct 02 11:21:23 PM UTC 24 Oct 02 11:23:58 PM UTC 24 10533191708 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1216247842 Oct 02 11:18:44 PM UTC 24 Oct 02 11:19:04 PM UTC 24 215886055 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.3856626601 Oct 02 11:19:03 PM UTC 24 Oct 02 11:19:04 PM UTC 24 38635606 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.1322898274 Oct 02 11:19:00 PM UTC 24 Oct 02 11:19:05 PM UTC 24 698212823 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4062309626 Oct 02 11:18:44 PM UTC 24 Oct 02 11:19:05 PM UTC 24 357365606 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.241818445 Oct 02 11:19:03 PM UTC 24 Oct 02 11:19:07 PM UTC 24 931253246 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3030257025 Oct 02 11:18:43 PM UTC 24 Oct 02 11:19:07 PM UTC 24 2900521264 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1400269205 Oct 02 11:19:05 PM UTC 24 Oct 02 11:19:07 PM UTC 24 57520540 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.4164815287 Oct 02 11:19:05 PM UTC 24 Oct 02 11:19:09 PM UTC 24 842821596 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3688939770 Oct 02 11:19:05 PM UTC 24 Oct 02 11:19:11 PM UTC 24 356839257 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3284175235 Oct 02 11:19:02 PM UTC 24 Oct 02 11:19:15 PM UTC 24 1495375578 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.4010231935 Oct 02 11:19:05 PM UTC 24 Oct 02 11:19:16 PM UTC 24 687700203 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1053105886 Oct 02 11:19:05 PM UTC 24 Oct 02 11:19:16 PM UTC 24 2953575716 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1420419965 Oct 02 11:18:44 PM UTC 24 Oct 02 11:19:16 PM UTC 24 1919857232 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.2267611786 Oct 02 11:19:08 PM UTC 24 Oct 02 11:19:19 PM UTC 24 578812330 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3621732723 Oct 02 11:19:05 PM UTC 24 Oct 02 11:19:20 PM UTC 24 319315234 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3178589369 Oct 02 11:18:56 PM UTC 24 Oct 02 11:19:21 PM UTC 24 9532511769 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1970600574 Oct 02 11:18:43 PM UTC 24 Oct 02 11:19:21 PM UTC 24 6366316601 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.519840050 Oct 02 11:19:05 PM UTC 24 Oct 02 11:19:21 PM UTC 24 1625524123 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1822301058 Oct 02 11:19:05 PM UTC 24 Oct 02 11:19:22 PM UTC 24 541669034 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2497878509 Oct 02 11:19:16 PM UTC 24 Oct 02 11:19:22 PM UTC 24 349648570 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.3078190740 Oct 02 11:18:44 PM UTC 24 Oct 02 11:19:23 PM UTC 24 863097519 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2183900896 Oct 02 11:19:23 PM UTC 24 Oct 02 11:19:25 PM UTC 24 31997595 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2501857369 Oct 02 11:19:23 PM UTC 24 Oct 02 11:19:27 PM UTC 24 122350185 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1503896149 Oct 02 11:18:43 PM UTC 24 Oct 02 11:19:30 PM UTC 24 22217847915 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.4210392260 Oct 02 11:18:48 PM UTC 24 Oct 02 11:19:37 PM UTC 24 763504472 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.657609250 Oct 02 11:19:08 PM UTC 24 Oct 02 11:19:45 PM UTC 24 4361319915 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1868900154 Oct 02 11:19:27 PM UTC 24 Oct 02 11:19:46 PM UTC 24 2668162798 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3587134287 Oct 02 11:18:46 PM UTC 24 Oct 02 11:19:47 PM UTC 24 3383911566 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2090336313 Oct 02 11:19:03 PM UTC 24 Oct 02 11:19:49 PM UTC 24 1474245881 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3773545224 Oct 02 11:19:32 PM UTC 24 Oct 02 11:19:49 PM UTC 24 2841004381 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1194454685 Oct 02 11:19:50 PM UTC 24 Oct 02 11:19:57 PM UTC 24 1987007139 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3127185728 Oct 02 11:19:21 PM UTC 24 Oct 02 11:19:58 PM UTC 24 4199063843 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1212942045 Oct 02 11:19:47 PM UTC 24 Oct 02 11:20:12 PM UTC 24 1742583692 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.4099398465 Oct 02 11:19:05 PM UTC 24 Oct 02 11:20:13 PM UTC 24 1021354449 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3890285459 Oct 02 11:19:59 PM UTC 24 Oct 02 11:20:16 PM UTC 24 304207890 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1643644476 Oct 02 11:20:13 PM UTC 24 Oct 02 11:20:17 PM UTC 24 129221140 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2012096892 Oct 02 11:19:05 PM UTC 24 Oct 02 11:20:17 PM UTC 24 22474983392 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2170845304 Oct 02 11:20:18 PM UTC 24 Oct 02 11:20:20 PM UTC 24 57563080 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1970891831 Oct 02 11:18:43 PM UTC 24 Oct 02 11:20:28 PM UTC 24 2356514021 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1025884840 Oct 02 11:19:23 PM UTC 24 Oct 02 11:20:47 PM UTC 24 856623842 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3002828932 Oct 02 11:19:39 PM UTC 24 Oct 02 11:20:47 PM UTC 24 818287766 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2238296506 Oct 02 11:19:08 PM UTC 24 Oct 02 11:20:49 PM UTC 24 14755663317 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1442137881 Oct 02 11:18:43 PM UTC 24 Oct 02 11:20:52 PM UTC 24 1571648869 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3962174121 Oct 02 11:19:08 PM UTC 24 Oct 02 11:21:03 PM UTC 24 2951352525 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.4102045835 Oct 02 11:18:46 PM UTC 24 Oct 02 11:21:13 PM UTC 24 1371300483 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2388169811 Oct 02 11:20:53 PM UTC 24 Oct 02 11:21:13 PM UTC 24 1441625910 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.3053735543 Oct 02 11:20:49 PM UTC 24 Oct 02 11:21:21 PM UTC 24 2946845587 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.627004288 Oct 02 11:19:58 PM UTC 24 Oct 02 11:21:26 PM UTC 24 11322925174 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.321636676 Oct 02 11:18:44 PM UTC 24 Oct 02 11:21:27 PM UTC 24 2634246305 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.1766444306 Oct 02 11:20:18 PM UTC 24 Oct 02 11:21:28 PM UTC 24 875957962 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1417735754 Oct 02 11:21:27 PM UTC 24 Oct 02 11:21:32 PM UTC 24 417833654 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3398164615 Oct 02 11:18:44 PM UTC 24 Oct 02 11:21:33 PM UTC 24 20027099453 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.3012359774 Oct 02 11:19:02 PM UTC 24 Oct 02 11:21:36 PM UTC 24 8994821612 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.872815702 Oct 02 11:21:04 PM UTC 24 Oct 02 11:21:39 PM UTC 24 3883722364 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.677409421 Oct 02 11:21:37 PM UTC 24 Oct 02 11:21:39 PM UTC 24 40095701 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.701231988 Oct 02 11:21:39 PM UTC 24 Oct 02 11:21:56 PM UTC 24 763969453 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.426869876 Oct 02 11:21:33 PM UTC 24 Oct 02 11:22:02 PM UTC 24 6266777637 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3962930932 Oct 02 11:20:47 PM UTC 24 Oct 02 11:22:19 PM UTC 24 1958947957 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3793073929 Oct 02 11:19:16 PM UTC 24 Oct 02 11:22:31 PM UTC 24 86396617991 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.923400059 Oct 02 11:19:05 PM UTC 24 Oct 02 11:22:32 PM UTC 24 4674416390 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.705700829 Oct 02 11:18:43 PM UTC 24 Oct 02 11:22:37 PM UTC 24 22549540209 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1336895993 Oct 02 11:22:20 PM UTC 24 Oct 02 11:22:39 PM UTC 24 4772398823 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3283534199 Oct 02 11:19:50 PM UTC 24 Oct 02 11:22:42 PM UTC 24 20209373545 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3485515490 Oct 02 11:19:18 PM UTC 24 Oct 02 11:22:54 PM UTC 24 30473300987 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.622946168 Oct 02 11:22:33 PM UTC 24 Oct 02 11:23:14 PM UTC 24 4477337999 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3673359321 Oct 02 11:19:25 PM UTC 24 Oct 02 11:23:27 PM UTC 24 16238922043 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.990531146 Oct 02 11:23:28 PM UTC 24 Oct 02 11:23:35 PM UTC 24 1538804003 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.860783243 Oct 02 11:19:12 PM UTC 24 Oct 02 11:23:35 PM UTC 24 8239393272 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3105395646 Oct 02 11:18:46 PM UTC 24 Oct 02 11:23:47 PM UTC 24 15762852294 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1274439327 Oct 02 11:22:40 PM UTC 24 Oct 02 11:23:51 PM UTC 24 42919018246 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1973205631 Oct 02 11:19:05 PM UTC 24 Oct 02 11:23:52 PM UTC 24 13775292600 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.2617389790 Oct 02 11:23:53 PM UTC 24 Oct 02 11:23:55 PM UTC 24 31574922 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.3901846269 Oct 02 11:21:29 PM UTC 24 Oct 02 11:23:56 PM UTC 24 4916028353 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.866546056 Oct 02 11:23:56 PM UTC 24 Oct 02 11:24:12 PM UTC 24 5358808094 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.670862081 Oct 02 11:19:05 PM UTC 24 Oct 02 11:23:57 PM UTC 24 16412785406 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2573133218 Oct 02 11:23:47 PM UTC 24 Oct 02 11:23:59 PM UTC 24 341445417 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.137694048 Oct 02 11:24:00 PM UTC 24 Oct 02 11:24:09 PM UTC 24 872399545 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.2995625633 Oct 02 11:22:38 PM UTC 24 Oct 02 11:24:21 PM UTC 24 784785792 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.982530560 Oct 02 11:18:43 PM UTC 24 Oct 02 11:24:30 PM UTC 24 15668026124 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3021160289 Oct 02 11:19:06 PM UTC 24 Oct 02 11:24:30 PM UTC 24 4695016816 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.4213377023 Oct 02 11:24:22 PM UTC 24 Oct 02 11:24:50 PM UTC 24 754421819 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.441153685 Oct 02 11:20:18 PM UTC 24 Oct 02 11:24:51 PM UTC 24 24795986890 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.3376063963 Oct 02 11:18:44 PM UTC 24 Oct 02 11:24:57 PM UTC 24 13093286483 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1066271183 Oct 02 11:23:36 PM UTC 24 Oct 02 11:25:04 PM UTC 24 5569116711 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2467546510 Oct 02 11:24:58 PM UTC 24 Oct 02 11:25:05 PM UTC 24 1352077960 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1607632494 Oct 02 11:23:15 PM UTC 24 Oct 02 11:25:12 PM UTC 24 1339518640 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.268567260 Oct 02 11:19:00 PM UTC 24 Oct 02 11:25:18 PM UTC 24 43132557890 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1916955393 Oct 02 11:24:13 PM UTC 24 Oct 02 11:25:51 PM UTC 24 3191774577 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1912232238 Oct 02 11:25:52 PM UTC 24 Oct 02 11:25:54 PM UTC 24 33988173 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3982847724 Oct 02 11:20:29 PM UTC 24 Oct 02 11:26:01 PM UTC 24 4719592638 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.2300984441 Oct 02 11:19:08 PM UTC 24 Oct 02 11:26:05 PM UTC 24 36217819834 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.4267460272 Oct 02 11:22:04 PM UTC 24 Oct 02 11:26:06 PM UTC 24 4492490349 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3242359405 Oct 02 11:19:29 PM UTC 24 Oct 02 11:26:07 PM UTC 24 59056922976 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.4246039933 Oct 02 11:24:31 PM UTC 24 Oct 02 11:26:23 PM UTC 24 9205574693 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1480708457 Oct 02 11:19:05 PM UTC 24 Oct 02 11:26:30 PM UTC 24 41635032064 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.4261827742 Oct 02 11:26:07 PM UTC 24 Oct 02 11:26:30 PM UTC 24 1095591910 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2830135432 Oct 02 11:23:36 PM UTC 24 Oct 02 11:26:31 PM UTC 24 38337443420 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.2476490092 Oct 02 11:25:05 PM UTC 24 Oct 02 11:26:34 PM UTC 24 4738524182 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3659218322 Oct 02 11:19:05 PM UTC 24 Oct 02 11:26:39 PM UTC 24 5910514466 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.911657215 Oct 02 11:26:02 PM UTC 24 Oct 02 11:26:40 PM UTC 24 1499948043 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.2198573630 Oct 02 11:26:31 PM UTC 24 Oct 02 11:26:40 PM UTC 24 2889141204 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.2779809793 Oct 02 11:24:51 PM UTC 24 Oct 02 11:26:44 PM UTC 24 520909720 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2581712119 Oct 02 11:26:41 PM UTC 24 Oct 02 11:26:47 PM UTC 24 697400684 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2695603315 Oct 02 11:26:32 PM UTC 24 Oct 02 11:27:10 PM UTC 24 726617749 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2459760975 Oct 02 11:27:10 PM UTC 24 Oct 02 11:27:23 PM UTC 24 249771391 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2982219143 Oct 02 11:25:55 PM UTC 24 Oct 02 11:27:23 PM UTC 24 808946536 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2620149304 Oct 02 11:27:24 PM UTC 24 Oct 02 11:27:26 PM UTC 24 57432679 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3213197191 Oct 02 11:26:41 PM UTC 24 Oct 02 11:27:39 PM UTC 24 3529204898 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3652882500 Oct 02 11:19:10 PM UTC 24 Oct 02 11:27:42 PM UTC 24 52314348892 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.2676443271 Oct 02 11:26:32 PM UTC 24 Oct 02 11:27:45 PM UTC 24 10572181545 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.952948338 Oct 02 11:27:27 PM UTC 24 Oct 02 11:27:59 PM UTC 24 1406468325 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.3256075313 Oct 02 11:22:43 PM UTC 24 Oct 02 11:28:00 PM UTC 24 39178161272 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.4109974841 Oct 02 11:18:46 PM UTC 24 Oct 02 11:28:01 PM UTC 24 71707217127 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.389109002 Oct 02 11:26:48 PM UTC 24 Oct 02 11:28:14 PM UTC 24 9461256860 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.890105501 Oct 02 11:28:02 PM UTC 24 Oct 02 11:28:15 PM UTC 24 2680709734 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3344656761 Oct 02 11:20:48 PM UTC 24 Oct 02 11:28:22 PM UTC 24 16171742384 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.3797211724 Oct 02 11:21:27 PM UTC 24 Oct 02 11:28:25 PM UTC 24 74680492242 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.152535080 Oct 02 11:23:58 PM UTC 24 Oct 02 11:28:29 PM UTC 24 12897425265 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1251184595 Oct 02 11:28:15 PM UTC 24 Oct 02 11:28:52 PM UTC 24 783237423 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.4067061837 Oct 02 11:18:44 PM UTC 24 Oct 02 11:28:57 PM UTC 24 4641984820 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.4167885882 Oct 02 11:28:53 PM UTC 24 Oct 02 11:28:59 PM UTC 24 1403920162 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.992260733 Oct 02 11:22:55 PM UTC 24 Oct 02 11:29:29 PM UTC 24 6668049708 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.359860317 Oct 02 11:25:13 PM UTC 24 Oct 02 11:29:37 PM UTC 24 4919115458 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.268508674 Oct 02 11:28:16 PM UTC 24 Oct 02 11:29:38 PM UTC 24 53773870605 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.2360659410 Oct 02 11:29:39 PM UTC 24 Oct 02 11:29:41 PM UTC 24 12351166 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.232694942 Oct 02 11:28:00 PM UTC 24 Oct 02 11:29:45 PM UTC 24 6557769389 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3387884612 Oct 02 11:29:30 PM UTC 24 Oct 02 11:29:47 PM UTC 24 2507980367 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2735248785 Oct 02 11:19:23 PM UTC 24 Oct 02 11:29:50 PM UTC 24 8223854200 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.3951742187 Oct 02 11:22:32 PM UTC 24 Oct 02 11:29:57 PM UTC 24 167439205594 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2995373409 Oct 02 11:19:05 PM UTC 24 Oct 02 11:30:01 PM UTC 24 22183477601 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2493817214 Oct 02 11:19:05 PM UTC 24 Oct 02 11:30:11 PM UTC 24 15023956375 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.2522195618 Oct 02 11:29:42 PM UTC 24 Oct 02 11:30:17 PM UTC 24 1083865669 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.792965591 Oct 02 11:18:56 PM UTC 24 Oct 02 11:30:20 PM UTC 24 230830276215 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.54196650 Oct 02 11:29:58 PM UTC 24 Oct 02 11:30:24 PM UTC 24 1256973009 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1484461078 Oct 02 11:26:07 PM UTC 24 Oct 02 11:30:31 PM UTC 24 32704573252 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.69383795 Oct 02 11:26:24 PM UTC 24 Oct 02 11:30:33 PM UTC 24 15097953507 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.1569050706 Oct 02 11:19:23 PM UTC 24 Oct 02 11:30:39 PM UTC 24 26433814853 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3430772780 Oct 02 11:24:31 PM UTC 24 Oct 02 11:30:39 PM UTC 24 8108246386 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.689921135 Oct 02 11:30:40 PM UTC 24 Oct 02 11:30:46 PM UTC 24 1674018142 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.842015215 Oct 02 11:25:04 PM UTC 24 Oct 02 11:30:54 PM UTC 24 30938078075 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.3552335395 Oct 02 11:24:10 PM UTC 24 Oct 02 11:31:04 PM UTC 24 66186758799 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1569204722 Oct 02 11:29:00 PM UTC 24 Oct 02 11:31:25 PM UTC 24 9340047598 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2226953007 Oct 02 11:30:18 PM UTC 24 Oct 02 11:31:25 PM UTC 24 7526447145 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.221557856 Oct 02 11:31:26 PM UTC 24 Oct 02 11:31:28 PM UTC 24 13996837 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.923721167 Oct 02 11:30:55 PM UTC 24 Oct 02 11:31:30 PM UTC 24 1081515204 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.64490228 Oct 02 11:18:56 PM UTC 24 Oct 02 11:31:35 PM UTC 24 17422562274 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.245270595 Oct 02 11:24:51 PM UTC 24 Oct 02 11:31:42 PM UTC 24 8198343705 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3261446010 Oct 02 11:30:12 PM UTC 24 Oct 02 11:31:42 PM UTC 24 1807952157 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.1360310338 Oct 02 11:30:20 PM UTC 24 Oct 02 11:31:48 PM UTC 24 11091345166 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2137029295 Oct 02 11:27:46 PM UTC 24 Oct 02 11:32:14 PM UTC 24 3300795947 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3481530385 Oct 02 11:30:47 PM UTC 24 Oct 02 11:32:17 PM UTC 24 3672090631 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4139138739 Oct 02 11:31:43 PM UTC 24 Oct 02 11:32:26 PM UTC 24 1021339354 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.926118862 Oct 02 11:26:45 PM UTC 24 Oct 02 11:32:34 PM UTC 24 57595356781 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.3865408787 Oct 02 11:19:05 PM UTC 24 Oct 02 11:32:37 PM UTC 24 24642950316 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3023177233 Oct 02 11:32:15 PM UTC 24 Oct 02 11:32:38 PM UTC 24 1493770882 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.639316131 Oct 02 11:21:14 PM UTC 24 Oct 02 11:32:39 PM UTC 24 55117744357 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.441285818 Oct 02 11:18:43 PM UTC 24 Oct 02 11:32:43 PM UTC 24 8222717642 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.18421981 Oct 02 11:32:39 PM UTC 24 Oct 02 11:32:43 PM UTC 24 387685939 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.272792911 Oct 02 11:31:26 PM UTC 24 Oct 02 11:32:48 PM UTC 24 813886771 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2979177749 Oct 02 11:31:49 PM UTC 24 Oct 02 11:33:08 PM UTC 24 838722888 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.4025671417 Oct 02 11:19:48 PM UTC 24 Oct 02 11:33:10 PM UTC 24 19785362913 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2127297452 Oct 02 11:33:09 PM UTC 24 Oct 02 11:33:11 PM UTC 24 16480260 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.2724160428 Oct 02 11:30:40 PM UTC 24 Oct 02 11:33:15 PM UTC 24 4031511665 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1155580904 Oct 02 11:32:17 PM UTC 24 Oct 02 11:33:18 PM UTC 24 31930627930 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.3998858220 Oct 02 11:33:11 PM UTC 24 Oct 02 11:33:27 PM UTC 24 3054047493 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1426234619 Oct 02 11:33:28 PM UTC 24 Oct 02 11:33:43 PM UTC 24 1802803553 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1880781451 Oct 02 11:33:50 PM UTC 24 Oct 02 11:33:59 PM UTC 24 1867770383 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.2731356140 Oct 02 11:19:16 PM UTC 24 Oct 02 11:34:12 PM UTC 24 3418537434 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.535895889 Oct 02 11:33:59 PM UTC 24 Oct 02 11:34:17 PM UTC 24 743159102 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1755338659 Oct 02 11:28:24 PM UTC 24 Oct 02 11:34:26 PM UTC 24 3817133789 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3605862855 Oct 02 11:28:01 PM UTC 24 Oct 02 11:34:29 PM UTC 24 71851039773 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1662047338 Oct 02 11:28:58 PM UTC 24 Oct 02 11:34:41 PM UTC 24 18532944192 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.659132498 Oct 02 11:34:42 PM UTC 24 Oct 02 11:34:48 PM UTC 24 356923114 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1994024370 Oct 02 11:18:44 PM UTC 24 Oct 02 11:35:15 PM UTC 24 12831310636 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1428249027 Oct 02 11:19:47 PM UTC 24 Oct 02 11:35:18 PM UTC 24 18603307310 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.1804404466 Oct 02 11:29:51 PM UTC 24 Oct 02 11:35:25 PM UTC 24 24062785542 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.2266907704 Oct 02 11:35:25 PM UTC 24 Oct 02 11:35:27 PM UTC 24 21455632 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2044400246 Oct 02 11:34:12 PM UTC 24 Oct 02 11:35:28 PM UTC 24 12219683714 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.309075974 Oct 02 11:35:15 PM UTC 24 Oct 02 11:35:31 PM UTC 24 926986479 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2398281431 Oct 02 11:32:45 PM UTC 24 Oct 02 11:35:41 PM UTC 24 2921092370 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1879576169 Oct 02 11:32:44 PM UTC 24 Oct 02 11:35:44 PM UTC 24 30795187540 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3423176793 Oct 02 11:35:45 PM UTC 24 Oct 02 11:35:57 PM UTC 24 2454426631 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.730219413 Oct 02 11:35:28 PM UTC 24 Oct 02 11:36:03 PM UTC 24 5120318544 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3739726503 Oct 02 11:33:18 PM UTC 24 Oct 02 11:36:29 PM UTC 24 2976852482 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1914728688 Oct 02 11:31:36 PM UTC 24 Oct 02 11:36:38 PM UTC 24 14107942790 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2126052257 Oct 02 11:36:04 PM UTC 24 Oct 02 11:37:00 PM UTC 24 731621611 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.277098962 Oct 02 11:18:43 PM UTC 24 Oct 02 11:37:02 PM UTC 24 85617355151 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3015154832 Oct 02 11:30:24 PM UTC 24 Oct 02 11:37:09 PM UTC 24 12982695232 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.474592178 Oct 02 11:35:42 PM UTC 24 Oct 02 11:37:42 PM UTC 24 12617518175 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.1831851665 Oct 02 11:19:00 PM UTC 24 Oct 02 11:37:47 PM UTC 24 13335892648 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2004668053 Oct 02 11:37:43 PM UTC 24 Oct 02 11:37:50 PM UTC 24 1301184389 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.915732848 Oct 02 11:21:14 PM UTC 24 Oct 02 11:37:56 PM UTC 24 83242297163 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.308530346 Oct 02 11:36:39 PM UTC 24 Oct 02 11:38:06 PM UTC 24 9182788834 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4235925650 Oct 02 11:30:02 PM UTC 24 Oct 02 11:38:23 PM UTC 24 78185172990 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.3081123946 Oct 02 11:28:30 PM UTC 24 Oct 02 11:38:25 PM UTC 24 177876891138 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.771231200 Oct 02 11:36:30 PM UTC 24 Oct 02 11:38:26 PM UTC 24 7111134205 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3547625476 Oct 02 11:38:24 PM UTC 24 Oct 02 11:38:26 PM UTC 24 26050430 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.78159143 Oct 02 11:35:29 PM UTC 24 Oct 02 11:38:37 PM UTC 24 3150904447 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4004642823 Oct 02 11:37:57 PM UTC 24 Oct 02 11:38:41 PM UTC 24 1012059916 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1697049173 Oct 02 11:34:17 PM UTC 24 Oct 02 11:38:41 PM UTC 24 3823494463 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1039216221 Oct 02 11:35:09 PM UTC 24 Oct 02 11:38:46 PM UTC 24 20792412681 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.4053402839 Oct 02 11:38:26 PM UTC 24 Oct 02 11:38:47 PM UTC 24 8920679898 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.29037335 Oct 02 11:31:30 PM UTC 24 Oct 02 11:38:58 PM UTC 24 58153023740 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3282248905 Oct 02 11:38:59 PM UTC 24 Oct 02 11:39:13 PM UTC 24 753652436 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.92796464 Oct 02 11:38:42 PM UTC 24 Oct 02 11:39:16 PM UTC 24 943926360 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3638516617 Oct 02 11:26:35 PM UTC 24 Oct 02 11:39:19 PM UTC 24 15097554475 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.425779809 Oct 02 11:33:44 PM UTC 24 Oct 02 11:39:21 PM UTC 24 6778972789 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1703733166 Oct 02 11:38:48 PM UTC 24 Oct 02 11:39:24 PM UTC 24 786651611 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.4115264888 Oct 02 11:39:22 PM UTC 24 Oct 02 11:39:27 PM UTC 24 1352508918 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.3849308142 Oct 02 11:23:57 PM UTC 24 Oct 02 11:39:40 PM UTC 24 137243831143 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1247915589 Oct 02 11:38:47 PM UTC 24 Oct 02 11:39:43 PM UTC 24 759110142 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2360343636 Oct 02 11:39:40 PM UTC 24 Oct 02 11:40:07 PM UTC 24 555322552 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2572638500 Oct 02 11:40:08 PM UTC 24 Oct 02 11:40:10 PM UTC 24 38152501 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3400676183 Oct 02 11:19:48 PM UTC 24 Oct 02 11:40:41 PM UTC 24 17626470689 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1015351382 Oct 02 11:32:27 PM UTC 24 Oct 02 11:40:46 PM UTC 24 9904066715 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3619337008 Oct 02 11:27:40 PM UTC 24 Oct 02 11:40:51 PM UTC 24 12694090650 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2504007600 Oct 02 11:32:40 PM UTC 24 Oct 02 11:40:52 PM UTC 24 82799115265 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2323655061 Oct 02 11:37:51 PM UTC 24 Oct 02 11:40:55 PM UTC 24 12873363012 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3978770787 Oct 02 11:21:40 PM UTC 24 Oct 02 11:40:57 PM UTC 24 19362871189 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3308859046 Oct 02 11:31:44 PM UTC 24 Oct 02 11:41:03 PM UTC 24 24821698797 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.3767418176 Oct 02 11:40:11 PM UTC 24 Oct 02 11:41:08 PM UTC 24 1649000601 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.818556391 Oct 02 11:40:53 PM UTC 24 Oct 02 11:41:41 PM UTC 24 458829344 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2124579128 Oct 02 11:34:49 PM UTC 24 Oct 02 11:41:54 PM UTC 24 129357855332 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3910058220 Oct 02 11:37:48 PM UTC 24 Oct 02 11:41:58 PM UTC 24 3945235383 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.204821550 Oct 02 11:29:46 PM UTC 24 Oct 02 11:42:01 PM UTC 24 9898391659 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.1451943842 Oct 02 11:32:35 PM UTC 24 Oct 02 11:42:02 PM UTC 24 7337621736 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3091980283 Oct 02 11:41:09 PM UTC 24 Oct 02 11:42:04 PM UTC 24 22921918345 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.77276221 Oct 02 11:23:57 PM UTC 24 Oct 02 11:42:07 PM UTC 24 67639488240 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.3652948199 Oct 02 11:42:02 PM UTC 24 Oct 02 11:42:07 PM UTC 24 359237328 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3824931116 Oct 02 11:35:58 PM UTC 24 Oct 02 11:42:33 PM UTC 24 14177561701 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.3496271216 Oct 02 11:42:34 PM UTC 24 Oct 02 11:42:36 PM UTC 24 47513645 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.2631632552 Oct 02 11:40:57 PM UTC 24 Oct 02 11:42:39 PM UTC 24 4014483788 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3373096334 Oct 02 11:39:27 PM UTC 24 Oct 02 11:42:41 PM UTC 24 10051977081 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3036334954 Oct 02 11:41:04 PM UTC 24 Oct 02 11:42:46 PM UTC 24 3120930611 ps
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