Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16000733

1

T3

146

T4

81

T6

662

full_word

141633512

1

T2

16

T3

33

T4

852

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	157633935	1			T2	16		T3	179		T4	933
auto[TlIntgErrCmd]	104	1			T118	4		T119	7		T120	7
auto[TlIntgErrData]	104	1			T118	6		T119	7		T120	11
auto[TlIntgErrBoth]	102	1			T118	10		T119	6		T120	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75644974

1

T2

16

T3

84

T4

448

auto[1]

81989271

1

T3

95

T4

485

T6

3465

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7821906	1			T3	70		T4	39		T6	341
auto[TlIntgErrNone]	partial	auto[1]	8178549	1			T3	76		T4	42		T6	321
auto[TlIntgErrNone]	full_word	auto[0]	67822920	1			T2	16		T3	14		T4	409
auto[TlIntgErrNone]	full_word	auto[1]	73810560	1			T3	19		T4	443		T6	3144
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T118	4		T119	2		T120	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T119	5		T120	5		T134	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T141	1		T139	2		T142	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T141	1		T143	2		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1			T118	2		T119	2		T120	4
auto[TlIntgErrData]	partial	auto[1]	53	1			T118	3		T119	4		T120	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T119	1		T120	3		T134	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T118	1		T120	1		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T118	4		T119	4		T120	1
auto[TlIntgErrBoth]	partial	auto[1]	43	1			T118	4		T119	2		T120	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T118	1		T136	1		T141	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T118	1		T136	1		T139	1