Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	987927	1			T3	6		T10	11		T32	269
auto[1]	10251595	1			T3	4		T10	7		T11	2578
auto[2]	768063	1			T3	4		T10	10		T32	153
auto[3]	9986258	1			T3	1		T10	7		T11	2566

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13957562	1			T10	19		T11	3436		T13	1581
auto[1]	2072558	1			T3	3		T10	7		T11	769
auto[2]	2093622	1			T3	2		T10	8		T11	758
auto[3]	3870101	1			T3	10		T10	1		T11	181

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8849750

1

T3

15

T10

35

T11

5144

auto[1]

13144093

1

T62

120721

T54

1

T55

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	368365	1			T10	9		T32	7		T8	8
auto[0]	auto[0]	auto[1]	37668	1			T3	1		T10	2		T32	37
auto[0]	auto[0]	auto[2]	37531	1			T32	42		T8	1		T54	10
auto[0]	auto[0]	auto[3]	52141	1			T3	5		T32	183		T8	1
auto[0]	auto[1]	auto[0]	3204902	1			T10	3		T11	1734		T13	799
auto[0]	auto[1]	auto[1]	337135	1			T3	1		T10	3		T11	382
auto[0]	auto[1]	auto[2]	334049	1			T3	1		T10	1		T11	371
auto[0]	auto[1]	auto[3]	205892	1			T3	2		T11	91		T28	3
auto[0]	auto[2]	auto[0]	267187	1			T10	6		T8	11		T9	9
auto[0]	auto[2]	auto[1]	30176	1			T3	1		T10	1		T8	1
auto[0]	auto[2]	auto[2]	30503	1			T3	1		T10	3		T32	33
auto[0]	auto[2]	auto[3]	39700	1			T3	2		T32	120		T19	1
auto[0]	auto[3]	auto[0]	3064506	1			T10	1		T11	1702		T13	782
auto[0]	auto[3]	auto[1]	317661	1			T10	1		T11	387		T28	18
auto[0]	auto[3]	auto[2]	334702	1			T10	4		T11	387		T28	20
auto[0]	auto[3]	auto[3]	187632	1			T3	1		T10	1		T11	90
auto[1]	auto[0]	auto[0]	16304	1			T63	279		T158	1082		T159	854
auto[1]	auto[0]	auto[1]	72685	1			T63	1300		T158	5079		T159	3692
auto[1]	auto[0]	auto[2]	73228	1			T63	1290		T158	5148		T159	3621
auto[1]	auto[0]	auto[3]	330005	1			T63	6135		T84	1		T96	1
auto[1]	auto[1]	auto[0]	3513174	1			T62	50173		T63	175		T105	56908
auto[1]	auto[1]	auto[1]	631926	1			T62	4478		T63	1543		T105	5081
auto[1]	auto[1]	auto[2]	604540	1			T62	5099		T63	866		T105	5705
auto[1]	auto[1]	auto[3]	1419977	1			T62	416		T63	6867		T105	539
auto[1]	auto[2]	auto[0]	13026	1			T63	169		T158	1057		T159	718
auto[1]	auto[2]	auto[1]	57452	1			T63	813		T158	4642		T159	3338
auto[1]	auto[2]	auto[2]	59773	1			T63	1274		T158	4358		T159	3085
auto[1]	auto[2]	auto[3]	270246	1			T63	5708		T158	19041		T159	13983
auto[1]	auto[3]	auto[0]	3510098	1			T62	50582		T55	1		T63	73
auto[1]	auto[3]	auto[1]	587855	1			T62	5055		T63	339		T105	5605
auto[1]	auto[3]	auto[2]	619296	1			T62	4492		T63	1469		T105	4969
auto[1]	auto[3]	auto[3]	1364508	1			T62	426		T54	1		T63	6662