Module Definition
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Module Instance : tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 5 5 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
oh_i[0] Yes Yes *T12,*T4,*T7 Yes T12,T4,T7 INPUT
oh_i[1] Unreachable Unreachable Unreachable INPUT
oh_i[8:2] Yes Yes T4,T7,T18 Yes T4,T7,T18 INPUT
addr_i[3:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
err_o Yes Yes T4,T7,T18 Yes T4,T7,T18 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%