Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	91.92	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1147827826	239365	0	0
ctrl_regwen_rd_A	1147827826	8237	0	0
exec_rd_A	1147827826	7460	0	0
exec_regwen_rd_A	1147827826	8187	0	0
readback_rd_A	1147827826	8147	0	0
readback_regwen_rd_A	1147827826	5132	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147827826	239365	0	0
T8	124635	0	0	0
T14	986	0	0	0
T19	294671	0	0	0
T24	62768	2495	0	0
T25	0	4559	0	0
T26	0	6345	0	0
T37	79167	0	0	0
T38	74222	0	0	0
T42	500700	0	0	0
T48	0	4758	0	0
T49	0	7429	0	0
T53	0	3804	0	0
T62	303101	0	0	0
T64	0	1868	0	0
T65	0	6498	0	0
T66	0	5345	0	0
T67	0	3876	0	0
T68	42133	0	0	0
T69	73063	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147827826	8237	0	0
T25	188477	214	0	0
T31	10988	0	0	0
T48	0	380	0	0
T51	525443	0	0	0
T53	0	169	0	0
T63	114498	0	0	0
T66	0	340	0	0
T105	324805	0	0	0
T106	669134	0	0	0
T121	0	163	0	0
T122	0	237	0	0
T123	0	282	0	0
T124	0	40	0	0
T125	0	356	0	0
T126	0	170	0	0
T127	74351	0	0	0
T128	34428	0	0	0
T129	66271	0	0	0
T130	1396	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147827826	7460	0	0
T25	188477	228	0	0
T31	10988	0	0	0
T48	0	244	0	0
T51	525443	0	0	0
T53	0	124	0	0
T63	114498	0	0	0
T66	0	370	0	0
T105	324805	0	0	0
T106	669134	0	0	0
T121	0	228	0	0
T122	0	188	0	0
T123	0	388	0	0
T124	0	81	0	0
T125	0	329	0	0
T126	0	228	0	0
T127	74351	0	0	0
T128	34428	0	0	0
T129	66271	0	0	0
T130	1396	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147827826	8187	0	0
T25	188477	211	0	0
T31	10988	0	0	0
T48	0	444	0	0
T51	525443	0	0	0
T53	0	165	0	0
T63	114498	0	0	0
T66	0	361	0	0
T105	324805	0	0	0
T106	669134	0	0	0
T121	0	189	0	0
T122	0	258	0	0
T123	0	371	0	0
T124	0	83	0	0
T125	0	374	0	0
T126	0	149	0	0
T127	74351	0	0	0
T128	34428	0	0	0
T129	66271	0	0	0
T130	1396	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147827826	8147	0	0
T25	188477	200	0	0
T31	10988	0	0	0
T48	0	306	0	0
T51	525443	0	0	0
T53	0	122	0	0
T63	114498	0	0	0
T66	0	349	0	0
T105	324805	0	0	0
T106	669134	0	0	0
T121	0	110	0	0
T122	0	206	0	0
T123	0	278	0	0
T127	74351	0	0	0
T128	34428	0	0	0
T129	66271	0	0	0
T130	1396	0	0	0
T131	0	98	0	0
T132	0	22	0	0
T133	0	5	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147827826	5132	0	0
T25	188477	199	0	0
T31	10988	0	0	0
T48	0	319	0	0
T51	525443	0	0	0
T53	0	108	0	0
T63	114498	0	0	0
T66	0	270	0	0
T105	324805	0	0	0
T106	669134	0	0	0
T121	0	98	0	0
T122	0	181	0	0
T123	0	254	0	0
T124	0	34	0	0
T125	0	231	0	0
T126	0	158	0	0
T127	74351	0	0	0
T128	34428	0	0	0
T129	66271	0	0	0
T130	1396	0	0	0