Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16654652

1

T2

82

T6

59

T7

148

full_word

149537203

1

T2

903

T4

54

T5

1690

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	166191545	1			T2	985		T4	54		T5	1690
auto[TlIntgErrCmd]	107	1			T113	6		T114	6		T115	1
auto[TlIntgErrData]	111	1			T113	7		T114	6		T115	5
auto[TlIntgErrBoth]	92	1			T113	7		T114	8		T115	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80124237

1

T2

505

T5

871

T6

285

auto[1]

86067618

1

T2

480

T4

54

T5

819

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8156855	1			T2	42		T6	33		T7	76
auto[TlIntgErrNone]	partial	auto[1]	8497509	1			T2	40		T6	26		T7	72
auto[TlIntgErrNone]	full_word	auto[0]	71967240	1			T2	463		T5	871		T6	252
auto[TlIntgErrNone]	full_word	auto[1]	77569941	1			T2	440		T4	54		T5	819
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T113	3		T114	4		T115	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T113	2		T114	2		T127	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T128	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T113	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T113	3		T114	5		T115	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T113	4		T114	1		T115	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T129	1		T131	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T133	1		T134	1		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T113	4		T114	3		T115	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T113	3		T114	5		T115	3
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T134	1		T135	1		T136	1