Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	871048	1			T7	227		T32	61		T37	5
auto[1]	10975884	1			T5	871		T7	59		T12	964
auto[2]	676016	1			T7	205		T32	44		T37	4
auto[3]	10684699	1			T5	818		T7	28		T12	945

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14097892	1			T5	1689		T7	388		T12	1329
auto[1]	2218347	1			T7	68		T12	254		T32	52
auto[2]	2261928	1			T7	58		T12	274		T32	48
auto[3]	4629480	1			T7	5		T12	52		T32	324

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8730177

1

T5

1689

T7

519

T12

1909

auto[1]

14477470

1

T68

1

T151

1

T69

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	328975	1			T7	185		T23	272		T24	18
auto[0]	auto[0]	auto[1]	33974	1			T7	24		T32	12		T37	1
auto[0]	auto[0]	auto[2]	33798	1			T7	17		T32	10		T23	33
auto[0]	auto[0]	auto[3]	52767	1			T7	1		T32	39		T37	4
auto[0]	auto[1]	auto[0]	3103677	1			T5	871		T7	22		T12	658
auto[0]	auto[1]	auto[1]	329198	1			T7	26		T12	128		T32	32
auto[0]	auto[1]	auto[2]	335375	1			T7	9		T12	148		T32	17
auto[0]	auto[1]	auto[3]	324221	1			T7	2		T12	30		T32	121
auto[0]	auto[2]	auto[0]	229900	1			T7	173		T37	1		T23	185
auto[0]	auto[2]	auto[1]	26415	1			T7	18		T37	2		T23	20
auto[0]	auto[2]	auto[2]	28279	1			T7	14		T32	8		T23	27
auto[0]	auto[2]	auto[3]	37607	1			T32	36		T37	1		T23	3
auto[0]	auto[3]	auto[0]	2921937	1			T5	818		T7	8		T12	671
auto[0]	auto[3]	auto[1]	315008	1			T12	126		T32	8		T23	9
auto[0]	auto[3]	auto[2]	335512	1			T7	18		T12	126		T32	13
auto[0]	auto[3]	auto[3]	293534	1			T7	2		T12	22		T32	128
auto[1]	auto[0]	auto[0]	14100	1			T70	91		T110	114		T150	863
auto[1]	auto[0]	auto[1]	62951	1			T70	527		T110	497		T150	3833
auto[1]	auto[0]	auto[2]	62894	1			T70	540		T110	451		T150	3874
auto[1]	auto[0]	auto[3]	281589	1			T70	2476		T110	2021		T150	17168
auto[1]	auto[1]	auto[0]	3747221	1			T68	1		T70	87		T107	50308
auto[1]	auto[1]	auto[1]	723665	1			T70	584		T107	4577		T108	5696
auto[1]	auto[1]	auto[2]	696661	1			T70	375		T94	1		T107	5024
auto[1]	auto[1]	auto[3]	1715866	1			T70	2846		T94	1		T107	489
auto[1]	auto[2]	auto[0]	10489	1			T70	72		T150	802		T152	261
auto[1]	auto[2]	auto[1]	46650	1			T70	335		T150	3541		T152	1197
auto[1]	auto[2]	auto[2]	54002	1			T70	500		T110	440		T150	3184
auto[1]	auto[2]	auto[3]	242674	1			T70	2431		T110	1891		T150	14496
auto[1]	auto[3]	auto[0]	3741593	1			T151	1		T70	22		T107	50122
auto[1]	auto[3]	auto[1]	680486	1			T70	152		T107	5058		T108	5624
auto[1]	auto[3]	auto[2]	715407	1			T70	591		T107	4498		T108	5667
auto[1]	auto[3]	auto[3]	1681222	1			T69	1		T70	2766		T94	1