Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	91.92	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1198358319	235849	0	0
ctrl_regwen_rd_A	1198358319	6060	0	0
exec_rd_A	1198358319	6099	0	0
exec_regwen_rd_A	1198358319	6188	0	0
readback_rd_A	1198358319	5921	0	0
readback_regwen_rd_A	1198358319	3490	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198358319	235849	0	0
T21	65897	0	0	0
T24	119661	3865	0	0
T25	58021	3525	0	0
T26	116079	3884	0	0
T27	0	10849	0	0
T28	0	4624	0	0
T35	34245	0	0	0
T41	131380	0	0	0
T42	0	8452	0	0
T43	0	6007	0	0
T60	54367	0	0	0
T61	106673	0	0	0
T62	79458	0	0	0
T67	0	9892	0	0
T71	0	4821	0	0
T72	0	2207	0	0
T73	1026	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198358319	6060	0	0
T10	929579	0	0	0
T21	65897	0	0	0
T25	58021	153	0	0
T26	116079	0	0	0
T35	34245	0	0	0
T41	131380	0	0	0
T43	0	379	0	0
T57	0	213	0	0
T60	54367	0	0	0
T61	106673	0	0	0
T62	79458	0	0	0
T63	67598	0	0	0
T67	0	669	0	0
T116	0	368	0	0
T117	0	46	0	0
T118	0	109	0	0
T119	0	177	0	0
T120	0	184	0	0
T121	0	126	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198358319	6099	0	0
T10	929579	0	0	0
T21	65897	0	0	0
T25	58021	188	0	0
T26	116079	0	0	0
T35	34245	0	0	0
T41	131380	0	0	0
T43	0	439	0	0
T57	0	215	0	0
T60	54367	0	0	0
T61	106673	0	0	0
T62	79458	0	0	0
T63	67598	0	0	0
T67	0	615	0	0
T116	0	322	0	0
T117	0	52	0	0
T118	0	148	0	0
T119	0	205	0	0
T120	0	200	0	0
T121	0	104	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198358319	6188	0	0
T10	929579	0	0	0
T21	65897	0	0	0
T25	58021	151	0	0
T26	116079	0	0	0
T35	34245	0	0	0
T41	131380	0	0	0
T43	0	386	0	0
T57	0	155	0	0
T60	54367	0	0	0
T61	106673	0	0	0
T62	79458	0	0	0
T63	67598	0	0	0
T67	0	729	0	0
T116	0	403	0	0
T117	0	56	0	0
T118	0	217	0	0
T119	0	221	0	0
T120	0	168	0	0
T121	0	124	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198358319	5921	0	0
T10	929579	0	0	0
T21	65897	0	0	0
T25	58021	105	0	0
T26	116079	0	0	0
T30	0	36	0	0
T35	34245	0	0	0
T41	131380	0	0	0
T43	0	385	0	0
T57	0	175	0	0
T60	54367	0	0	0
T61	106673	0	0	0
T62	79458	0	0	0
T63	67598	0	0	0
T67	0	616	0	0
T116	0	280	0	0
T117	0	34	0	0
T118	0	99	0	0
T122	0	124	0	0
T123	0	120	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1198358319	3490	0	0
T10	929579	0	0	0
T21	65897	0	0	0
T25	58021	102	0	0
T26	116079	0	0	0
T35	34245	0	0	0
T41	131380	0	0	0
T43	0	360	0	0
T57	0	176	0	0
T60	54367	0	0	0
T61	106673	0	0	0
T62	79458	0	0	0
T63	67598	0	0	0
T67	0	525	0	0
T116	0	291	0	0
T117	0	53	0	0
T118	0	72	0	0
T119	0	182	0	0
T120	0	167	0	0
T121	0	112	0	0