Unified Coverage Report :: Module :: tlul_lc_gate

Module : tlul_lc_gate

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.13	88.24	94.44		57.14	79.17	66.67

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate	92.33	100.00	100.00		100.00	95.00	66.67

---

Module Instance : tb.dut.u_tlul_lc_gate

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.33	100.00	100.00		100.00	95.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	100.00		100.00	96.43	88.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	91.92	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h	100.00	100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d	100.00	100.00
u_err_en_sync	100.00	100.00					100.00
u_state_regs	100.00	100.00				100.00	100.00
u_tlul_err_resp	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		51	45	88.24
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
ALWAYS	152	3	3	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
ALWAYS	161	6	6	100.00
ALWAYS	172	28	22	78.57
ALWAYS	238	10	10	100.00

91                        // Assign signals on the device side.
92         1/1            assign tl_h2d_o = tl_h2d_int[NumGatesPerDirection];
           Tests:       T1 T2 T3 
93         1/1            assign tl_d2h_int[NumGatesPerDirection] = tl_d2h_i;
           Tests:       T1 T2 T3 
94                      
95                        ///////////////////////////
96                        // Host Side Interposing //
97                        ///////////////////////////
98                      
99                        // Encoding generated with:
100                       // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \
101                       //      -s 3379253306 --language=sv
102                       //
103                       // Hamming distance histogram:
104                       //
105                       //  0: --
106                       //  1: --
107                       //  2: --
108                       //  3: --
109                       //  4: --
110                       //  5: |||||||||||||||||||| (66.67%)
111                       //  6: |||||||||| (33.33%)
112                       //  7: --
113                       //  8: --
114                       //
115                       // Minimum Hamming distance: 5
116                       // Maximum Hamming distance: 6
117                       // Minimum Hamming weight: 3
118                       // Maximum Hamming weight: 5
119                       //
120                       // Encoding generated with:
121                       // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \
122                       //      -s 686407169 --language=sv
123                       //
124                       // Hamming distance histogram:
125                       //
126                       //  0: --
127                       //  1: --
128                       //  2: --
129                       //  3: --
130                       //  4: --
131                       //  5: |||||||||||||||||||| (60.00%)
132                       //  6: ||||||||||||| (40.00%)
133                       //  7: --
134                       //  8: --
135                       //  9: --
136                       //
137                       // Minimum Hamming distance: 5
138                       // Maximum Hamming distance: 6
139                       // Minimum Hamming weight: 3
140                       // Maximum Hamming weight: 6
141                       //
142                       localparam int StateWidth = 9;
143                       typedef enum logic [StateWidth-1:0] {
144                         StActive = 9'b100100001,
145                         StOutstanding = 9'b011100111,
146                         StFlush = 9'b001001100,
147                         StError = 9'b010111010,
148                         StErrorOutstanding = 9'b100010110
149                       } state_e;
150                     
151                       state_e state_d, state_q;
152        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError):
152.1                   `ifdef SIMULATION                                   
152.2                       prim_sparse_fsm_flop #(                           
152.3                         .StateEnumT(state_e),                            
152.4                         .Width($bits(state_e)),                          
152.5                         .ResetValue($bits(state_e)'(StError)),          
152.6                         .EnableAlertTriggerSVA(1), 
152.7                         .CustomForceName("state_q")          
152.8                       ) u_state_regs (                                        
152.9                         .clk_i   ( clk_i   ),                           
152.10                        .rst_ni  ( rst_ni ),                           
152.11                        .state_i ( state_d     ),                           
152.12                        .state_o (         )                            
152.13                      );                                                
152.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
152.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
152.16     1/1                state_q <= StError;                                
           Tests:       T1 T2 T3 
152.17                      end else begin                                    
152.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
152.19                      end                                               
152.20                    end  
152.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
152.22                      else begin                                                                           
152.23                        `ifdef UVM                                                                               
152.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
152.25                                              "../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv", 152, "", 1);                                
152.26                  `else                                                                                    
152.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
152.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
152.29                  `endif                                                              
152.30                      end 
152.31                    `else                                               
152.32                      prim_sparse_fsm_flop #(                           
152.33                        .StateEnumT(state_e),                            
152.34                        .Width($bits(state_e)),                          
152.35                        .ResetValue($bits(state_e)'(StError)),          
152.36                        .EnableAlertTriggerSVA(1)  
152.37                      ) u_state_regs (                                        
152.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
152.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
152.40                        .state_i ( state_d     ),                           
152.41                        .state_o ( state_q     )                            
152.42                      );                                                
152.43                    `endif153                     
154                       logic [prim_util_pkg::vbits(Outstanding+1)-1:0] outstanding_txn;
155                       logic a_ack;
156                       logic d_ack;
157        1/1            assign a_ack = tl_h2d_i.a_valid & tl_d2h_o.a_ready;
           Tests:       T1 T2 T3 
158        1/1            assign d_ack = tl_h2d_i.d_ready & tl_d2h_o.d_valid;
           Tests:       T1 T2 T3 
159                     
160                       always_ff @(posedge clk_i or negedge rst_ni) begin
161        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
162        1/1                outstanding_txn <= '0;
           Tests:       T1 T2 T3 
163        1/1              end else if (a_ack && !d_ack) begin
           Tests:       T1 T2 T3 
164        1/1                outstanding_txn <= outstanding_txn + 1'b1;
           Tests:       T2 T4 T5 
165        1/1              end else if (d_ack && !a_ack) begin
           Tests:       T1 T2 T3 
166        1/1                outstanding_txn <= outstanding_txn - 1'b1;
           Tests:       T2 T4 T5 
167                         end
                        MISSING_ELSE
168                       end
169                     
170                       logic block_cmd;
171                       always_comb begin
172        1/1              block_cmd = '0;
           Tests:       T1 T2 T3 
173        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
174        1/1              err_en = Off;
           Tests:       T1 T2 T3 
175        1/1              err_o = '0;
           Tests:       T1 T2 T3 
176        1/1              flush_ack_o = '0;
           Tests:       T1 T2 T3 
177        1/1              resp_pending_o = 1'b0;
           Tests:       T1 T2 T3 
178                     
179        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
180                           StActive: begin
181        1/1                  if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin
           Tests:       T1 T2 T3 
182        1/1                    state_d = StOutstanding;
           Tests:       T2 T4 T6 
183                             end
                        MISSING_ELSE
184        1/1                  if (outstanding_txn != '0) begin
           Tests:       T1 T2 T3 
185        1/1                    resp_pending_o = 1'b1;
           Tests:       T4 T5 T7 
186                             end
                        MISSING_ELSE
187                           end
188                     
189                           StOutstanding: begin
190        1/1                  block_cmd = 1'b1;
           Tests:       T2 T6 T8 
191        1/1                  if (outstanding_txn == '0) begin
           Tests:       T2 T6 T8 
192        1/1                    state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush;
           Tests:       T2 T6 T8 
193                             end else begin
194        1/1                    resp_pending_o = 1'b1;
           Tests:       T9 T10 T11 
195                             end
196                           end
197                     
198                           StFlush: begin
199        0/1     ==>          block_cmd = 1'b1;
200        0/1     ==>          flush_ack_o = 1'b1;
201        0/1     ==>          if (lc_tx_test_false_loose(lc_en_i)) begin
202        0/1     ==>            state_d = StError;
203        0/1     ==>          end else if (!flush_req_i) begin
204        0/1     ==>            state_d = StActive;
205                             end
                   ==>  MISSING_ELSE
206                           end
207                     
208                           StError: begin
209        1/1                  err_en = On;
           Tests:       T1 T2 T3 
210        1/1                  if (lc_tx_test_true_strict(lc_en_i)) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = StErrorOutstanding;
           Tests:       T1 T2 T3 
212                             end
                        MISSING_ELSE
213                           end
214                     
215                           StErrorOutstanding: begin
216        1/1                  err_en = On;
           Tests:       T1 T2 T3 
217        1/1                  block_cmd = 1'b1;
           Tests:       T1 T2 T3 
218        1/1                  if (outstanding_txn == '0) begin
           Tests:       T1 T2 T3 
219        1/1                    state_d = StActive;
           Tests:       T1 T2 T3 
220                             end
                   ==>  MISSING_ELSE
221                           end
222                     
223                           default: begin
224                             err_o = 1'b1;
225                             err_en = On;
226                           end
227                     
228                         endcase // unique case (state_q)
229                       end
230                     
231                     
232                       // At the host side, we interpose the ready / valid signals so that we can return a bus error
233                       // in case the lc signal is not set to ON. Note that this logic does not have to be duplicated
234                       // since erroring back is considered a convenience feature so that the bus does not lock up.
235                       tl_h2d_t tl_h2d_error;
236                       tl_d2h_t tl_d2h_error;
237                       always_comb begin
238        1/1              tl_h2d_int[0] = tl_h2d_i;
           Tests:       T1 T2 T3 
239        1/1              tl_d2h_o      = tl_d2h_int[0];
           Tests:       T1 T2 T3 
240        1/1              tl_h2d_error  = '0;
           Tests:       T1 T2 T3 
241                     
242        1/1              if (lc_tx_test_true_loose(err_en)) begin
           Tests:       T1 T2 T3 
243        1/1                tl_h2d_error  = tl_h2d_i;
           Tests:       T1 T2 T3 
244        1/1                tl_d2h_o      = tl_d2h_error;
           Tests:       T1 T2 T3 
245                         end
                        MISSING_ELSE
246                     
247        1/1              if (block_cmd) begin
           Tests:       T1 T2 T3 
248        1/1                tl_d2h_o.a_ready = 1'b0;
           Tests:       T1 T2 T3 
249        1/1                tl_h2d_int[0].a_valid = 1'b0;
           Tests:       T1 T2 T3 
250        1/1                tl_h2d_error.a_valid = 1'b0;
           Tests:       T1 T2 T3 
251                         end
                        MISSING_ELSE

---

Cond Coverage for Module : tlul_lc_gate

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       157
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T5

 LINE       158
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       163
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T12
1	1	Covered	T2,T4,T5

 LINE       165
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T12
1	1	Covered	T2,T4,T5

 LINE       184
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       191
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T9,T10,T11
1	Covered	T2,T6,T8

 LINE       218
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

FSM Coverage for Module : tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	7	4	57.14
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StActive	204	Covered	T1,T2,T3
StError	192	Covered	T1,T2,T3
StErrorOutstanding	211	Covered	T1,T2,T3
StFlush	192	Not Covered
StOutstanding	182	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
StActive->StOutstanding	182	Covered	T2,T6,T8
StError->StErrorOutstanding	211	Covered	T1,T2,T3
StErrorOutstanding->StActive	219	Covered	T1,T2,T3
StFlush->StActive	204	Not Covered
StFlush->StError	202	Not Covered
StOutstanding->StError	192	Covered	T2,T6,T8
StOutstanding->StFlush	192	Not Covered

---

Branch Coverage for Module : tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		24	19	79.17
IF	152	2	2	100.00
IF	161	4	4	100.00
CASE	179	14	9	64.29
IF	242	2	2	100.00
IF	247	2	2	100.00

152          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

161            if (!rst_ni) begin
               -1-  
162              outstanding_txn <= '0;
                 ==>
163            end else if (a_ack && !d_ack) begin
                        -2-  
164              outstanding_txn <= outstanding_txn + 1'b1;
                 ==>
165            end else if (d_ack && !a_ack) begin
                        -3-  
166              outstanding_txn <= outstanding_txn - 1'b1;
                 ==>
167            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

179            unique case (state_q)
                      -1-  
180              StActive: begin
181                if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin
                   -2-  
182                  state_d = StOutstanding;
                     ==>
183                end
                   MISSING_ELSE
                   ==>
184                if (outstanding_txn != '0) begin
                   -3-  
185                  resp_pending_o = 1'b1;
                     ==>
186                end
                   MISSING_ELSE
                   ==>
187              end
188        
189              StOutstanding: begin
190                block_cmd = 1'b1;
191                if (outstanding_txn == '0) begin
                   -4-  
192                  state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush;
                     ==>
193                end else begin
194                  resp_pending_o = 1'b1;
                     ==>
195                end
196              end
197        
198              StFlush: begin
199                block_cmd = 1'b1;
200                flush_ack_o = 1'b1;
201                if (lc_tx_test_false_loose(lc_en_i)) begin
                   -5-  
202                  state_d = StError;
                     ==>
203                end else if (!flush_req_i) begin
                            -6-  
204                  state_d = StActive;
                     ==>
205                end
                   MISSING_ELSE
                   ==>
206              end
207        
208              StError: begin
209                err_en = On;
210                if (lc_tx_test_true_strict(lc_en_i)) begin
                   -7-  
211                  state_d = StErrorOutstanding;
                     ==>
212                end
                   MISSING_ELSE
                   ==>
213              end
214        
215              StErrorOutstanding: begin
216                err_en = On;
217                block_cmd = 1'b1;
218                if (outstanding_txn == '0) begin
                   -8-  
219                  state_d = StActive;
                     ==>
220                end
                   MISSING_ELSE
                   ==>
221              end
222        
223              default: begin
224                err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StActive	1	-	-	-	-	-	-	Covered	T2,T4,T6
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T3
StActive	-	1	-	-	-	-	-	Covered	T4,T5,T7
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T3
StOutstanding	-	-	1	-	-	-	-	Covered	T2,T6,T8
StOutstanding	-	-	0	-	-	-	-	Covered	T9,T10,T11
StFlush	-	-	-	1	-	-	-	Not Covered
StFlush	-	-	-	0	1	-	-	Not Covered
StFlush	-	-	-	0	0	-	-	Not Covered
StError	-	-	-	-	-	1	-	Covered	T1,T2,T3
StError	-	-	-	-	-	0	-	Covered	T2,T6,T8
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Not Covered

242            if (lc_tx_test_true_loose(err_en)) begin
               -1-  
243              tl_h2d_error  = tl_h2d_i;
                 ==>
244              tl_d2h_o      = tl_d2h_error;
245            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

247            if (block_cmd) begin
               -1-  
248              tl_d2h_o.a_ready = 1'b0;
                 ==>
249              tl_h2d_int[0].a_valid = 1'b0;
250              tl_h2d_error.a_valid = 1'b0;
251            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_lc_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	1186639916	0	0	0
SizeOutstandingTxn_A	1186639916	1186530814	0	0
u_state_regs_A	1186639916	1186530814	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186639916	0	0	0

SizeOutstandingTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186639916	1186530814	0	0
T1	881	806	0	0
T2	20184	14994	0	0
T3	33575	33500	0	0
T4	65883	65816	0	0
T5	67780	67715	0	0
T6	8664	6050	0	0
T7	44464	44409	0	0
T12	68618	68556	0	0
T13	38121	38055	0	0
T14	1046	994	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186639916	1186530814	0	0
T1	881	806	0	0
T2	20184	14994	0	0
T3	33575	33500	0	0
T4	65883	65816	0	0
T5	67780	67715	0	0
T6	8664	6050	0	0
T7	44464	44409	0	0
T12	68618	68556	0	0
T13	38121	38055	0	0
T14	1046	994	0	0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate

	Line No.	Total	Covered	Percent
TOTAL		45	45	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
ALWAYS	152	3	3	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
ALWAYS	161	6	6	100.00
ALWAYS	172	22	22	100.00
ALWAYS	238	10	10	100.00

91                        // Assign signals on the device side.
92         1/1            assign tl_h2d_o = tl_h2d_int[NumGatesPerDirection];
           Tests:       T1 T2 T3 
93         1/1            assign tl_d2h_int[NumGatesPerDirection] = tl_d2h_i;
           Tests:       T1 T2 T3 
94                      
95                        ///////////////////////////
96                        // Host Side Interposing //
97                        ///////////////////////////
98                      
99                        // Encoding generated with:
100                       // $ ./util/design/sparse-fsm-encode.py -d 5 -m 4 -n 8 \
101                       //      -s 3379253306 --language=sv
102                       //
103                       // Hamming distance histogram:
104                       //
105                       //  0: --
106                       //  1: --
107                       //  2: --
108                       //  3: --
109                       //  4: --
110                       //  5: |||||||||||||||||||| (66.67%)
111                       //  6: |||||||||| (33.33%)
112                       //  7: --
113                       //  8: --
114                       //
115                       // Minimum Hamming distance: 5
116                       // Maximum Hamming distance: 6
117                       // Minimum Hamming weight: 3
118                       // Maximum Hamming weight: 5
119                       //
120                       // Encoding generated with:
121                       // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \
122                       //      -s 686407169 --language=sv
123                       //
124                       // Hamming distance histogram:
125                       //
126                       //  0: --
127                       //  1: --
128                       //  2: --
129                       //  3: --
130                       //  4: --
131                       //  5: |||||||||||||||||||| (60.00%)
132                       //  6: ||||||||||||| (40.00%)
133                       //  7: --
134                       //  8: --
135                       //  9: --
136                       //
137                       // Minimum Hamming distance: 5
138                       // Maximum Hamming distance: 6
139                       // Minimum Hamming weight: 3
140                       // Maximum Hamming weight: 6
141                       //
142                       localparam int StateWidth = 9;
143                       typedef enum logic [StateWidth-1:0] {
144                         StActive = 9'b100100001,
145                         StOutstanding = 9'b011100111,
146                         StFlush = 9'b001001100,
147                         StError = 9'b010111010,
148                         StErrorOutstanding = 9'b100010110
149                       } state_e;
150                     
151                       state_e state_d, state_q;
152        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError):
152.1                   `ifdef SIMULATION                                   
152.2                       prim_sparse_fsm_flop #(                           
152.3                         .StateEnumT(state_e),                            
152.4                         .Width($bits(state_e)),                          
152.5                         .ResetValue($bits(state_e)'(StError)),          
152.6                         .EnableAlertTriggerSVA(1), 
152.7                         .CustomForceName("state_q")          
152.8                       ) u_state_regs (                                        
152.9                         .clk_i   ( clk_i   ),                           
152.10                        .rst_ni  ( rst_ni ),                           
152.11                        .state_i ( state_d     ),                           
152.12                        .state_o (         )                            
152.13                      );                                                
152.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
152.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
152.16     1/1                state_q <= StError;                                
           Tests:       T1 T2 T3 
152.17                      end else begin                                    
152.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
152.19                      end                                               
152.20                    end  
152.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
152.22                      else begin                                                                           
152.23                        `ifdef UVM                                                                               
152.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
152.25                                              "../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv", 152, "", 1);                                
152.26                  `else                                                                                    
152.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
152.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
152.29                  `endif                                                              
152.30                      end 
152.31                    `else                                               
152.32                      prim_sparse_fsm_flop #(                           
152.33                        .StateEnumT(state_e),                            
152.34                        .Width($bits(state_e)),                          
152.35                        .ResetValue($bits(state_e)'(StError)),          
152.36                        .EnableAlertTriggerSVA(1)  
152.37                      ) u_state_regs (                                        
152.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
152.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
152.40                        .state_i ( state_d     ),                           
152.41                        .state_o ( state_q     )                            
152.42                      );                                                
152.43                    `endif153                     
154                       logic [prim_util_pkg::vbits(Outstanding+1)-1:0] outstanding_txn;
155                       logic a_ack;
156                       logic d_ack;
157        1/1            assign a_ack = tl_h2d_i.a_valid & tl_d2h_o.a_ready;
           Tests:       T1 T2 T3 
158        1/1            assign d_ack = tl_h2d_i.d_ready & tl_d2h_o.d_valid;
           Tests:       T1 T2 T3 
159                     
160                       always_ff @(posedge clk_i or negedge rst_ni) begin
161        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
162        1/1                outstanding_txn <= '0;
           Tests:       T1 T2 T3 
163        1/1              end else if (a_ack && !d_ack) begin
           Tests:       T1 T2 T3 
164        1/1                outstanding_txn <= outstanding_txn + 1'b1;
           Tests:       T2 T4 T5 
165        1/1              end else if (d_ack && !a_ack) begin
           Tests:       T1 T2 T3 
166        1/1                outstanding_txn <= outstanding_txn - 1'b1;
           Tests:       T2 T4 T5 
167                         end
                        MISSING_ELSE
168                       end
169                     
170                       logic block_cmd;
171                       always_comb begin
172        1/1              block_cmd = '0;
           Tests:       T1 T2 T3 
173        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
174        1/1              err_en = Off;
           Tests:       T1 T2 T3 
175        1/1              err_o = '0;
           Tests:       T1 T2 T3 
176        1/1              flush_ack_o = '0;
           Tests:       T1 T2 T3 
177        1/1              resp_pending_o = 1'b0;
           Tests:       T1 T2 T3 
178                     
179        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
180                           StActive: begin
181        1/1                  if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin
           Tests:       T1 T2 T3 
182        1/1                    state_d = StOutstanding;
           Tests:       T2 T4 T6 
183                             end
                        MISSING_ELSE
184        1/1                  if (outstanding_txn != '0) begin
           Tests:       T1 T2 T3 
185        1/1                    resp_pending_o = 1'b1;
           Tests:       T4 T5 T7 
186                             end
                        MISSING_ELSE
187                           end
188                     
189                           StOutstanding: begin
190        1/1                  block_cmd = 1'b1;
           Tests:       T2 T6 T8 
191        1/1                  if (outstanding_txn == '0) begin
           Tests:       T2 T6 T8 
192        1/1                    state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush;
           Tests:       T2 T6 T8 
193                             end else begin
194        1/1                    resp_pending_o = 1'b1;
           Tests:       T9 T10 T11 
195                             end
196                           end
197                     
198                           StFlush: begin
199        excluded             block_cmd = 1'b1;
Exclude Annotation: VC_COV_UNR
200        excluded             flush_ack_o = 1'b1;
Exclude Annotation: VC_COV_UNR
201        excluded             if (lc_tx_test_false_loose(lc_en_i)) begin
Exclude Annotation: VC_COV_UNR
202        excluded               state_d = StError;
Exclude Annotation: VC_COV_UNR
203        excluded             end else if (!flush_req_i) begin
Exclude Annotation: VC_COV_UNR
204        excluded               state_d = StActive;
Exclude Annotation: VC_COV_UNR
205                             end
                   ==>  MISSING_ELSE
206                           end
207                     
208                           StError: begin
209        1/1                  err_en = On;
           Tests:       T1 T2 T3 
210        1/1                  if (lc_tx_test_true_strict(lc_en_i)) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = StErrorOutstanding;
           Tests:       T1 T2 T3 
212                             end
                        MISSING_ELSE
213                           end
214                     
215                           StErrorOutstanding: begin
216        1/1                  err_en = On;
           Tests:       T1 T2 T3 
217        1/1                  block_cmd = 1'b1;
           Tests:       T1 T2 T3 
218        1/1                  if (outstanding_txn == '0) begin
           Tests:       T1 T2 T3 
219        1/1                    state_d = StActive;
           Tests:       T1 T2 T3 
220                             end
                   ==>  MISSING_ELSE
221                           end
222                     
223                           default: begin
224                             err_o = 1'b1;
Exclude Annotation: VC_COV_UNR
225                             err_en = On;
Exclude Annotation: VC_COV_UNR
226                           end
227                     
228                         endcase // unique case (state_q)
229                       end
230                     
231                     
232                       // At the host side, we interpose the ready / valid signals so that we can return a bus error
233                       // in case the lc signal is not set to ON. Note that this logic does not have to be duplicated
234                       // since erroring back is considered a convenience feature so that the bus does not lock up.
235                       tl_h2d_t tl_h2d_error;
236                       tl_d2h_t tl_d2h_error;
237                       always_comb begin
238        1/1              tl_h2d_int[0] = tl_h2d_i;
           Tests:       T1 T2 T3 
239        1/1              tl_d2h_o      = tl_d2h_int[0];
           Tests:       T1 T2 T3 
240        1/1              tl_h2d_error  = '0;
           Tests:       T1 T2 T3 
241                     
242        1/1              if (lc_tx_test_true_loose(err_en)) begin
           Tests:       T1 T2 T3 
243        1/1                tl_h2d_error  = tl_h2d_i;
           Tests:       T1 T2 T3 
244        1/1                tl_d2h_o      = tl_d2h_error;
           Tests:       T1 T2 T3 
245                         end
                        MISSING_ELSE
246                     
247        1/1              if (block_cmd) begin
           Tests:       T1 T2 T3 
248        1/1                tl_d2h_o.a_ready = 1'b0;
           Tests:       T1 T2 T3 
249        1/1                tl_h2d_int[0].a_valid = 1'b0;
           Tests:       T1 T2 T3 
250        1/1                tl_h2d_error.a_valid = 1'b0;
           Tests:       T1 T2 T3 
251                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       157
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T5

 LINE       158
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       163
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T12
1	1	Covered	T2,T4,T5

 LINE       165
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T12
1	1	Covered	T2,T4,T5

 LINE       184
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       191
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T9,T10,T11
1	Covered	T2,T6,T8

 LINE       218
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
 Exclude Annotation: [LOWRISK] This happens in the 1st cycle after exiting reset. In order to cover it, need to drive TL items during reset, which isn't supported in the agent.

-1-	Status	Tests
0	Excluded
1	Excluded	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests	Exclude Annotation
StActive	204	Covered	T1,T2,T3
StError	192	Covered	T1,T2,T3
StErrorOutstanding	211	Covered	T1,T2,T3
StFlush	192	Excluded		VC_COV_UNR
StOutstanding	182	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
StActive->StOutstanding	182	Covered	T2,T6,T8
StError->StErrorOutstanding	211	Covered	T1,T2,T3
StErrorOutstanding->StActive	219	Covered	T1,T2,T3
StFlush->StActive	204	Excluded
StFlush->StError	202	Excluded
StOutstanding->StError	192	Covered	T2,T6,T8
StOutstanding->StFlush	192	Excluded

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
IF	152	2	2	100.00
IF	161	4	4	100.00
CASE	179	10	9	90.00
IF	242	2	2	100.00
IF	247	2	2	100.00

152          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StError)
             -1-                                                                       
             ==>                                                                       
             ==>                                                                       

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

161            if (!rst_ni) begin
               -1-  
162              outstanding_txn <= '0;
                 ==>
163            end else if (a_ack && !d_ack) begin
                        -2-  
164              outstanding_txn <= outstanding_txn + 1'b1;
                 ==>
165            end else if (d_ack && !a_ack) begin
                        -3-  
166              outstanding_txn <= outstanding_txn - 1'b1;
                 ==>
167            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

179            unique case (state_q)
                      -1-  
180              StActive: begin
181                if (lc_tx_test_false_loose(lc_en_i) || flush_req_i) begin
                   -2-  
182                  state_d = StOutstanding;
                     ==>
183                end
                   MISSING_ELSE
                   ==>
184                if (outstanding_txn != '0) begin
                   -3-  
185                  resp_pending_o = 1'b1;
                     ==>
186                end
                   MISSING_ELSE
                   ==>
187              end
188        
189              StOutstanding: begin
190                block_cmd = 1'b1;
191                if (outstanding_txn == '0) begin
                   -4-  
192                  state_d = lc_tx_test_false_loose(lc_en_i) ? StError : StFlush;
                     ==>
193                end else begin
194                  resp_pending_o = 1'b1;
                     ==>
195                end
196              end
197        
198              StFlush: begin
199                block_cmd = 1'b1;
200                flush_ack_o = 1'b1;
201                if (lc_tx_test_false_loose(lc_en_i)) begin
                   -5-  
202                  state_d = StError;
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
203                end else if (!flush_req_i) begin
                            -6-  
204                  state_d = StActive;
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
205                end
                   MISSING_ELSE
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR
206              end
207        
208              StError: begin
209                err_en = On;
210                if (lc_tx_test_true_strict(lc_en_i)) begin
                   -7-  
211                  state_d = StErrorOutstanding;
                     ==>
212                end
                   MISSING_ELSE
                   ==>
213              end
214        
215              StErrorOutstanding: begin
216                err_en = On;
217                block_cmd = 1'b1;
218                if (outstanding_txn == '0) begin
                   -8-  
219                  state_d = StActive;
                     ==>
220                end
                   MISSING_ELSE
                   ==>
221              end
222        
223              default: begin
224                err_o = 1'b1;
                   ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
StActive	1	-	-	-	-	-	-	Covered	T2,T4,T6
StActive	0	-	-	-	-	-	-	Covered	T1,T2,T3
StActive	-	1	-	-	-	-	-	Covered	T4,T5,T7
StActive	-	0	-	-	-	-	-	Covered	T1,T2,T3
StOutstanding	-	-	1	-	-	-	-	Covered	T2,T6,T8
StOutstanding	-	-	0	-	-	-	-	Covered	T9,T10,T11
StFlush	-	-	-	1	-	-	-	Excluded		VC_COV_UNR
StFlush	-	-	-	0	1	-	-	Excluded		VC_COV_UNR
StFlush	-	-	-	0	0	-	-	Excluded		VC_COV_UNR
StError	-	-	-	-	-	1	-	Covered	T1,T2,T3
StError	-	-	-	-	-	0	-	Covered	T2,T6,T8
StErrorOutstanding	-	-	-	-	-	-	1	Covered	T1,T2,T3
StErrorOutstanding	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

242            if (lc_tx_test_true_loose(err_en)) begin
               -1-  
243              tl_h2d_error  = tl_h2d_i;
                 ==>
244              tl_d2h_o      = tl_d2h_error;
245            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

247            if (block_cmd) begin
               -1-  
248              tl_d2h_o.a_ready = 1'b0;
                 ==>
249              tl_h2d_int[0].a_valid = 1'b0;
250              tl_h2d_error.a_valid = 1'b0;
251            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStandingOvfl_A	1186639916	0	0	0
SizeOutstandingTxn_A	1186639916	1186530814	0	0
u_state_regs_A	1186639916	1186530814	0	0

OutStandingOvfl_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186639916	0	0	0

SizeOutstandingTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186639916	1186530814	0	0
T1	881	806	0	0
T2	20184	14994	0	0
T3	33575	33500	0	0
T4	65883	65816	0	0
T5	67780	67715	0	0
T6	8664	6050	0	0
T7	44464	44409	0	0
T12	68618	68556	0	0
T13	38121	38055	0	0
T14	1046	994	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1186639916	1186530814	0	0
T1	881	806	0	0
T2	20184	14994	0	0
T3	33575	33500	0	0
T4	65883	65816	0	0
T5	67780	67715	0	0
T6	8664	6050	0	0
T7	44464	44409	0	0
T12	68618	68556	0	0
T13	38121	38055	0	0
T14	1046	994	0	0