Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15745640

1

T1

20

T3

84

T6

1063

full_word

156080418

1

T1

72

T3

895

T4

26

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	171825798	1			T1	92		T3	979		T4	26
auto[TlIntgErrCmd]	87	1			T134	7		T135	1		T136	6
auto[TlIntgErrData]	75	1			T134	6		T135	4		T136	7
auto[TlIntgErrBoth]	98	1			T134	7		T135	5		T136	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82908912

1

T1

48

T3

499

T6

594

auto[1]

88917146

1

T1

44

T3

480

T4

26

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7693741	1			T1	6		T3	43		T6	218
auto[TlIntgErrNone]	partial	auto[1]	8051667	1			T1	14		T3	41		T6	845
auto[TlIntgErrNone]	full_word	auto[0]	75215053	1			T1	42		T3	456		T6	376
auto[TlIntgErrNone]	full_word	auto[1]	80865337	1			T1	30		T3	439		T4	26
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T134	2		T135	1		T136	6
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T134	4		T147	2		T142	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T134	1		T149	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T142	2		T145	2		T146	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T134	4		T135	2		T136	2
auto[TlIntgErrData]	partial	auto[1]	33	1			T134	2		T135	2		T136	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T150	1		T151	2		T152	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T136	1		T145	1		T150	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T134	3		T135	1		T136	3
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T134	3		T135	4		T136	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T134	1		T136	1		T145	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T153	1		T145	1		T146	1