Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
partial 16675241 1 T1 2342 T2 572 T5 68
full_word 155206309 1 T1 534 T2 6016 T4 7998


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] 171881280 1 T1 2876 T2 6588 T4 7998
auto[TlIntgErrCmd] 91 1 T58 7 T59 4 T60 4
auto[TlIntgErrData] 90 1 T58 6 T59 2 T60 2
auto[TlIntgErrBoth] 89 1 T58 7 T59 4 T60 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 82778261 1 T1 1427 T2 3284 T4 4007
auto[1] 89103289 1 T1 1449 T2 3304 T4 3991


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_type   cp_num_num_enable_bytes   cp_write   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] partial auto[0] 8155134 1 T1 1146 T2 279 T5 36
auto[TlIntgErrNone] partial auto[1] 8519864 1 T1 1196 T2 293 T5 32
auto[TlIntgErrNone] full_word auto[0] 74623014 1 T1 281 T2 3005 T4 4007
auto[TlIntgErrNone] full_word auto[1] 80583268 1 T1 253 T2 3011 T4 3991
auto[TlIntgErrCmd] partial auto[0] 26 1 T58 2 T59 1 T60 1
auto[TlIntgErrCmd] partial auto[1] 58 1 T58 5 T59 3 T60 2
auto[TlIntgErrCmd] full_word auto[0] 3 1 T60 1 T132 1 T138 1
auto[TlIntgErrCmd] full_word auto[1] 4 1 T139 1 T140 1 T141 1
auto[TlIntgErrData] partial auto[0] 38 1 T58 1 T59 2 T60 1
auto[TlIntgErrData] partial auto[1] 40 1 T58 2 T60 1 T130 1
auto[TlIntgErrData] full_word auto[0] 5 1 T58 1 T131 1 T139 1
auto[TlIntgErrData] full_word auto[1] 7 1 T58 2 T132 1 T136 1
auto[TlIntgErrBoth] partial auto[0] 36 1 T58 2 T60 1 T130 2
auto[TlIntgErrBoth] partial auto[1] 45 1 T58 3 T59 4 T60 3
auto[TlIntgErrBoth] full_word auto[0] 5 1 T132 1 T136 1 T140 1
auto[TlIntgErrBoth] full_word auto[1] 3 1 T58 2 T140 1 - -