Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_lib_0/dv_base_env_cov.sv

13 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::size_over_max 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::PutFullData_mask_not_match_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::addr_not_align_mask 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::addr_not_align_size 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::invalid_a_opcode 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::mask_not_in_enabled_lanes 100.00 1 100 1 64 64
uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::size_over_max 100.00 1 100 1 64 64



Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::PutFullData_mask_not_match_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::addr_not_align_mask
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::addr_not_align_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::invalid_a_opcode
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_outstanding_item_w_same_addr_cov_obj
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::mask_not_in_enabled_lanes
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::size_over_max
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::PutFullData_mask_not_match_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::PutFullData_mask_not_match_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::PutFullData_mask_not_match_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::addr_not_align_mask
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::addr_not_align_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::addr_not_align_mask
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::addr_not_align_size
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::addr_not_align_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::addr_not_align_size
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::invalid_a_opcode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::invalid_a_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::invalid_a_opcode
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::mask_not_in_enabled_lanes
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::mask_not_in_enabled_lanes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::mask_not_in_enabled_lanes
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::size_over_max
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::size_over_max

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::size_over_max
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 31885 1 T12 976 T24 424 T25 266
rising 31891 1 T12 976 T24 424 T25 266


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 235007 1 T12 6749 T24 3310 T25 1915
auto[1] 36909 1 T12 1134 T24 496 T25 305


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 57127 1 T12 1654 T24 840 T25 456
rising 57129 1 T12 1654 T24 840 T25 457


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 189917 1 T12 5547 T24 2607 T25 1527
auto[1] 81999 1 T12 2336 T24 1199 T25 693


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 57127 1 T12 1654 T24 840 T25 456
rising 57129 1 T12 1654 T24 840 T25 457


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 189917 1 T12 5547 T24 2607 T25 1527
auto[1] 81999 1 T12 2336 T24 1199 T25 693


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 61977 1 T12 1752 T24 886 T25 511
rising 61978 1 T12 1752 T24 886 T25 511


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 175823 1 T12 5239 T24 2465 T25 1423
auto[1] 96093 1 T12 2644 T24 1341 T25 797


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 776236 1 T10 2 T38 33173 T105 21605
rising 776241 1 T10 2 T38 33173 T105 21606


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 174356343 1 T1 2876 T2 6588 T4 7998
auto[1] 1201721 1 T10 2 T38 58191 T105 38052


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 44535 1 T12 1272 T24 613 T25 370
rising 44533 1 T12 1272 T24 612 T25 369


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 215804 1 T12 6261 T24 3032 T25 1747
auto[1] 56112 1 T12 1622 T24 774 T25 473


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 44141 1 T12 1269 T24 586 T25 347
rising 44143 1 T12 1269 T24 587 T25 347


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 216603 1 T12 6289 T24 3067 T25 1790
auto[1] 55313 1 T12 1594 T24 739 T25 430


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 35108 1 T12 1086 T24 559 T25 407
rising 35097 1 T12 1085 T24 559 T25 407


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 242224 1 T12 7263 T24 3664 T25 2548
auto[1] 41881 1 T12 1296 T24 673 T25 496


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 67835 1 T12 2022 T24 1020 T25 721
rising 67832 1 T12 2022 T24 1020 T25 720


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 169295 1 T12 5094 T24 2671 T25 1874
auto[1] 114810 1 T12 3465 T24 1666 T25 1170


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 67835 1 T12 2022 T24 1020 T25 721
rising 67832 1 T12 2022 T24 1020 T25 720


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 169295 1 T12 5094 T24 2671 T25 1874
auto[1] 114810 1 T12 3465 T24 1666 T25 1170


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 69553 1 T12 2082 T24 1047 T25 725
rising 69570 1 T12 2083 T24 1046 T25 726


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 152552 1 T12 4569 T24 2405 T25 1751
auto[1] 131553 1 T12 3990 T24 1932 T25 1293


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 49948 1 T12 1506 T24 763 T25 523
rising 49946 1 T12 1505 T24 763 T25 524


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 218828 1 T12 6629 T24 3319 T25 2334
auto[1] 65277 1 T12 1930 T24 1018 T25 710


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
falling 50889 1 T12 1522 T24 781 T25 563
rising 50880 1 T12 1522 T24 780 T25 563


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 217558 1 T12 6547 T24 3331 T25 2299
auto[1] 66547 1 T12 2012 T24 1006 T25 745