Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	837082	1			T40	842		T9	10		T41	202
auto[1]	10869666	1			T1	47		T11	368		T31	1327
auto[2]	632685	1			T40	737		T9	4		T41	214
auto[3]	10565501	1			T1	43		T11	334		T31	1350

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14226236	1			T1	56		T11	702		T31	2215
auto[1]	2180882	1			T1	15		T31	212		T35	4
auto[2]	2205178	1			T1	14		T31	223		T35	12
auto[3]	4292638	1			T1	5		T31	27		T35	16

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8850563

1

T1

90

T11

702

T31

2677

auto[1]

14054371

1

T43

1

T61

1

T95

7

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	333137	1			T40	31		T9	7		T41	7
auto[0]	auto[0]	auto[1]	34328	1			T40	137		T9	1		T41	23
auto[0]	auto[0]	auto[2]	34561	1			T40	133		T9	2		T41	32
auto[0]	auto[0]	auto[3]	79450	1			T40	541		T41	140		T54	1
auto[0]	auto[1]	auto[0]	3180634	1			T1	35		T11	368		T31	1097
auto[0]	auto[1]	auto[1]	331864	1			T1	6		T31	100		T35	1
auto[0]	auto[1]	auto[2]	336049	1			T1	5		T31	111		T35	9
auto[0]	auto[1]	auto[3]	272198	1			T1	1		T31	19		T35	7
auto[0]	auto[2]	auto[0]	239107	1			T40	26		T9	4		T41	5
auto[0]	auto[2]	auto[1]	29373	1			T40	101		T41	15		T81	162
auto[0]	auto[2]	auto[2]	27498	1			T40	117		T41	31		T54	11
auto[0]	auto[2]	auto[3]	58217	1			T40	493		T41	163		T54	1
auto[0]	auto[3]	auto[0]	3002387	1			T1	21		T11	334		T31	1118
auto[0]	auto[3]	auto[1]	315685	1			T1	9		T31	112		T35	3
auto[0]	auto[3]	auto[2]	332990	1			T1	9		T31	112		T35	3
auto[0]	auto[3]	auto[3]	243085	1			T1	4		T31	8		T35	9
auto[1]	auto[0]	auto[0]	11736	1			T120	94		T125	765		T168	1119
auto[1]	auto[0]	auto[1]	53111	1			T120	476		T125	3517		T168	4943
auto[1]	auto[0]	auto[2]	53026	1			T120	466		T125	3568		T168	4981
auto[1]	auto[0]	auto[3]	237733	1			T95	6		T120	2034		T125	15861
auto[1]	auto[1]	auto[0]	3726457	1			T61	1		T64	62492		T27	1
auto[1]	auto[1]	auto[1]	705531	1			T64	5807		T120	1547		T121	11800
auto[1]	auto[1]	auto[2]	683988	1			T64	6303		T120	808		T121	13029
auto[1]	auto[1]	auto[3]	1632945	1			T95	1		T64	579		T120	6891
auto[1]	auto[2]	auto[0]	9105	1			T125	717		T168	1046		T169	174
auto[1]	auto[2]	auto[1]	40316	1			T125	3289		T168	4607		T169	703
auto[1]	auto[2]	auto[2]	41781	1			T120	414		T125	2937		T168	4180
auto[1]	auto[2]	auto[3]	187288	1			T120	1840		T125	13382		T168	19170
auto[1]	auto[3]	auto[0]	3723673	1			T43	1		T64	61839		T120	75
auto[1]	auto[3]	auto[1]	670674	1			T64	6220		T120	398		T121	13122
auto[1]	auto[3]	auto[2]	695285	1			T64	5633		T120	1485		T121	11843
auto[1]	auto[3]	auto[3]	1581722	1			T64	583		T120	6710		T121	52707