Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	855669	1			T1	76		T2	25		T10	4313
auto[1]	10650510	1			T1	202		T2	217		T4	4007
auto[2]	653353	1			T1	50		T2	15		T10	3065
auto[3]	10374451	1			T1	184		T2	182		T4	3990

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14271466	1			T1	12		T2	314		T4	7997
auto[1]	2085418	1			T1	59		T2	48		T5	44
auto[2]	2132655	1			T1	70		T2	67		T5	51
auto[3]	4044444	1			T1	371		T2	10		T5	4

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9272918

1

T1

512

T2

439

T4

7996

auto[1]

13261065

1

T4

1

T9

1

T10

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	347868	1			T1	4		T2	22		T10	1
auto[0]	auto[0]	auto[1]	36103	1			T1	12		T10	40		T38	1
auto[0]	auto[0]	auto[2]	36051	1			T1	10		T2	2		T10	45
auto[0]	auto[0]	auto[3]	59285	1			T1	50		T2	1		T10	4223
auto[0]	auto[1]	auto[0]	3242437	1			T1	7		T2	166		T4	4007
auto[0]	auto[1]	auto[1]	340633	1			T1	36		T2	33		T5	16
auto[0]	auto[1]	auto[2]	353217	1			T1	18		T2	13		T5	29
auto[0]	auto[1]	auto[3]	372956	1			T1	141		T2	5		T9	185
auto[0]	auto[2]	auto[0]	265618	1			T10	3		T32	1		T78	853
auto[0]	auto[2]	auto[1]	30229	1			T10	357		T78	70		T151	6
auto[0]	auto[2]	auto[2]	28552	1			T1	9		T2	13		T10	27
auto[0]	auto[2]	auto[3]	40357	1			T1	41		T2	2		T10	2678
auto[0]	auto[3]	auto[0]	3099750	1			T1	1		T2	126		T4	3989
auto[0]	auto[3]	auto[1]	333460	1			T1	11		T2	15		T5	28
auto[0]	auto[3]	auto[2]	350814	1			T1	33		T2	39		T5	22
auto[0]	auto[3]	auto[3]	335588	1			T1	139		T2	2		T5	4
auto[1]	auto[0]	auto[0]	12555	1			T38	857		T105	532		T27	1
auto[1]	auto[0]	auto[1]	56007	1			T38	3563		T105	2360		T107	3981
auto[1]	auto[0]	auto[2]	56130	1			T38	3601		T105	2420		T107	3932
auto[1]	auto[0]	auto[3]	251670	1			T10	4		T38	16147		T105	10597
auto[1]	auto[1]	auto[0]	3648944	1			T9	1		T35	60277		T38	148
auto[1]	auto[1]	auto[1]	645882	1			T35	6000		T38	3675		T61	4942
auto[1]	auto[1]	auto[2]	629210	1			T35	6118		T38	597		T61	5514
auto[1]	auto[1]	auto[3]	1417231	1			T35	571		T38	16166		T61	561
auto[1]	auto[2]	auto[0]	8092	1			T38	690		T105	481		T152	1
auto[1]	auto[2]	auto[1]	36363	1			T38	3400		T105	2167		T107	3566
auto[1]	auto[2]	auto[2]	44166	1			T38	2426		T105	1493		T107	2727
auto[1]	auto[2]	auto[3]	199976	1			T38	10843		T105	7129		T107	11607
auto[1]	auto[3]	auto[0]	3646202	1			T4	1		T35	61224		T37	1
auto[1]	auto[3]	auto[1]	606741	1			T35	5992		T38	336		T61	5531
auto[1]	auto[3]	auto[2]	634515	1			T35	5958		T38	2409		T61	4988
auto[1]	auto[3]	auto[3]	1367381	1			T35	561		T38	11232		T61	506