Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Module :
prim_lc_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2697 |
2697 |
0 |
0 |
T1 |
3 |
3 |
0 |
0 |
T2 |
3 |
3 |
0 |
0 |
T3 |
3 |
3 |
0 |
0 |
T4 |
3 |
3 |
0 |
0 |
T5 |
3 |
3 |
0 |
0 |
T6 |
3 |
3 |
0 |
0 |
T9 |
3 |
3 |
0 |
0 |
T10 |
3 |
3 |
0 |
0 |
T11 |
3 |
3 |
0 |
0 |
T12 |
3 |
3 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
254250 |
254094 |
0 |
0 |
T2 |
220461 |
220290 |
0 |
0 |
T3 |
103188 |
102906 |
0 |
0 |
T4 |
224112 |
223923 |
0 |
0 |
T5 |
1571115 |
1570773 |
0 |
0 |
T6 |
55218 |
47457 |
0 |
0 |
T9 |
234246 |
234051 |
0 |
0 |
T10 |
802485 |
802323 |
0 |
0 |
T11 |
5319 |
5100 |
0 |
0 |
T12 |
743337 |
742992 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
5394 |
T1 |
169500 |
169390 |
0 |
6 |
T2 |
146974 |
146854 |
0 |
6 |
T3 |
68792 |
68598 |
0 |
6 |
T4 |
149408 |
149276 |
0 |
6 |
T5 |
1047410 |
1047054 |
0 |
6 |
T6 |
36812 |
31392 |
0 |
6 |
T9 |
156164 |
156028 |
0 |
6 |
T10 |
534990 |
534876 |
0 |
6 |
T11 |
3546 |
3394 |
0 |
6 |
T12 |
495558 |
495262 |
0 |
6 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1161669134 |
1161565366 |
0 |
0 |
T1 |
84750 |
84698 |
0 |
0 |
T2 |
73487 |
73430 |
0 |
0 |
T3 |
34396 |
34302 |
0 |
0 |
T4 |
74704 |
74641 |
0 |
0 |
T5 |
523705 |
523591 |
0 |
0 |
T6 |
18406 |
15819 |
0 |
0 |
T9 |
78082 |
78017 |
0 |
0 |
T10 |
267495 |
267441 |
0 |
0 |
T11 |
1773 |
1700 |
0 |
0 |
T12 |
247779 |
247664 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_lc_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_prim_lc_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1161669134 |
1161565366 |
0 |
0 |
T1 |
84750 |
84698 |
0 |
0 |
T2 |
73487 |
73430 |
0 |
0 |
T3 |
34396 |
34302 |
0 |
0 |
T4 |
74704 |
74641 |
0 |
0 |
T5 |
523705 |
523591 |
0 |
0 |
T6 |
18406 |
15819 |
0 |
0 |
T9 |
78082 |
78017 |
0 |
0 |
T10 |
267495 |
267441 |
0 |
0 |
T11 |
1773 |
1700 |
0 |
0 |
T12 |
247779 |
247664 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1161669134 |
1161551869 |
0 |
2697 |
T1 |
84750 |
84695 |
0 |
3 |
T2 |
73487 |
73427 |
0 |
3 |
T3 |
34396 |
34299 |
0 |
3 |
T4 |
74704 |
74638 |
0 |
3 |
T5 |
523705 |
523527 |
0 |
3 |
T6 |
18406 |
15696 |
0 |
3 |
T9 |
78082 |
78014 |
0 |
3 |
T10 |
267495 |
267438 |
0 |
3 |
T11 |
1773 |
1697 |
0 |
3 |
T12 |
247779 |
247631 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1161669134 |
1161565366 |
0 |
0 |
T1 |
84750 |
84698 |
0 |
0 |
T2 |
73487 |
73430 |
0 |
0 |
T3 |
34396 |
34302 |
0 |
0 |
T4 |
74704 |
74641 |
0 |
0 |
T5 |
523705 |
523591 |
0 |
0 |
T6 |
18406 |
15819 |
0 |
0 |
T9 |
78082 |
78017 |
0 |
0 |
T10 |
267495 |
267441 |
0 |
0 |
T11 |
1773 |
1700 |
0 |
0 |
T12 |
247779 |
247664 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1161669134 |
1161565366 |
0 |
0 |
T1 |
84750 |
84698 |
0 |
0 |
T2 |
73487 |
73430 |
0 |
0 |
T3 |
34396 |
34302 |
0 |
0 |
T4 |
74704 |
74641 |
0 |
0 |
T5 |
523705 |
523591 |
0 |
0 |
T6 |
18406 |
15819 |
0 |
0 |
T9 |
78082 |
78017 |
0 |
0 |
T10 |
267495 |
267441 |
0 |
0 |
T11 |
1773 |
1700 |
0 |
0 |
T12 |
247779 |
247664 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
899 |
899 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1161669134 |
1161565366 |
0 |
0 |
T1 |
84750 |
84698 |
0 |
0 |
T2 |
73487 |
73430 |
0 |
0 |
T3 |
34396 |
34302 |
0 |
0 |
T4 |
74704 |
74641 |
0 |
0 |
T5 |
523705 |
523591 |
0 |
0 |
T6 |
18406 |
15819 |
0 |
0 |
T9 |
78082 |
78017 |
0 |
0 |
T10 |
267495 |
267441 |
0 |
0 |
T11 |
1773 |
1700 |
0 |
0 |
T12 |
247779 |
247664 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1161669134 |
1161551869 |
0 |
2697 |
T1 |
84750 |
84695 |
0 |
3 |
T2 |
73487 |
73427 |
0 |
3 |
T3 |
34396 |
34299 |
0 |
3 |
T4 |
74704 |
74638 |
0 |
3 |
T5 |
523705 |
523527 |
0 |
3 |
T6 |
18406 |
15696 |
0 |
3 |
T9 |
78082 |
78014 |
0 |
3 |
T10 |
267495 |
267438 |
0 |
3 |
T11 |
1773 |
1697 |
0 |
3 |
T12 |
247779 |
247631 |
0 |
3 |