Unified Coverage Report :: Module :: prim_lfsr

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lfsr	100.00			100.00

---

Module Instance : tb.dut.u_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	6	6	100.00
Total Bits	136	136	100.00
Total Bits 0->1	68	68	100.00
Total Bits 1->0	68	68	100.00

Ports	6	6	100.00
Port Bits	136	136	100.00
Port Bits 0->1	68	68	100.00
Port Bits 1->0	68	68	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T5,T6,T12	Yes	T1,T2,T3	INPUT
seed_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
seed_i[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T4	INPUT
lfsr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
entropy_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT