Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1172650405	260564	0	0
ctrl_regwen_rd_A	1172650405	2443	0	0
exec_rd_A	1172650405	2237	0	0
exec_regwen_rd_A	1172650405	2666	0	0
readback_rd_A	1172650405	1707	0	0
readback_regwen_rd_A	1172650405	1581	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172650405	260564	0	0
T7	441504	0	0	0
T12	247779	8656	0	0
T24	0	3833	0	0
T25	0	2409	0	0
T26	464929	0	0	0
T28	34431	0	0	0
T32	81757	0	0	0
T33	691687	0	0	0
T34	40141	0	0	0
T35	434953	0	0	0
T36	75129	0	0	0
T37	75634	0	0	0
T47	0	10678	0	0
T49	0	4988	0	0
T53	0	10810	0	0
T56	0	8555	0	0
T65	0	10081	0	0
T66	0	1900	0	0
T67	0	3311	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172650405	2443	0	0
T58	0	27	0	0
T71	0	2	0	0
T110	25486	91	0	0
T111	0	220	0	0
T112	0	83	0	0
T113	0	170	0	0
T114	0	118	0	0
T115	0	254	0	0
T116	0	127	0	0
T117	0	524	0	0
T118	127691	0	0	0
T119	1288	0	0	0
T120	378123	0	0	0
T121	115328	0	0	0
T122	244256	0	0	0
T123	429016	0	0	0
T124	746288	0	0	0
T125	73550	0	0	0
T126	660607	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172650405	2237	0	0
T58	0	40	0	0
T71	0	7	0	0
T110	25486	86	0	0
T111	0	246	0	0
T112	0	124	0	0
T113	0	153	0	0
T114	0	91	0	0
T115	0	161	0	0
T116	0	88	0	0
T117	0	445	0	0
T118	127691	0	0	0
T119	1288	0	0	0
T120	378123	0	0	0
T121	115328	0	0	0
T122	244256	0	0	0
T123	429016	0	0	0
T124	746288	0	0	0
T125	73550	0	0	0
T126	660607	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172650405	2666	0	0
T58	0	63	0	0
T71	0	7	0	0
T110	25486	153	0	0
T111	0	198	0	0
T112	0	138	0	0
T113	0	194	0	0
T114	0	165	0	0
T115	0	259	0	0
T116	0	151	0	0
T117	0	514	0	0
T118	127691	0	0	0
T119	1288	0	0	0
T120	378123	0	0	0
T121	115328	0	0	0
T122	244256	0	0	0
T123	429016	0	0	0
T124	746288	0	0	0
T125	73550	0	0	0
T126	660607	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172650405	1707	0	0
T110	25486	66	0	0
T111	0	264	0	0
T112	0	97	0	0
T113	0	201	0	0
T114	0	116	0	0
T115	0	190	0	0
T116	0	111	0	0
T117	0	510	0	0
T118	127691	0	0	0
T119	1288	0	0	0
T120	378123	0	0	0
T121	115328	0	0	0
T122	244256	0	0	0
T123	429016	0	0	0
T124	746288	0	0	0
T125	73550	0	0	0
T126	660607	0	0	0
T127	0	17	0	0
T128	0	22	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1172650405	1581	0	0
T58	0	4	0	0
T110	25486	53	0	0
T111	0	180	0	0
T112	0	133	0	0
T113	0	158	0	0
T114	0	139	0	0
T115	0	211	0	0
T116	0	132	0	0
T117	0	460	0	0
T118	127691	0	0	0
T119	1288	0	0	0
T120	378123	0	0	0
T121	115328	0	0	0
T122	244256	0	0	0
T123	429016	0	0	0
T124	746288	0	0	0
T125	73550	0	0	0
T126	660607	0	0	0
T127	0	10	0	0