Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.50	100.00	91.92	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1195514048	252083	0	0
ctrl_regwen_rd_A	1195514048	5960	0	0
exec_rd_A	1195514048	5408	0	0
exec_regwen_rd_A	1195514048	5811	0	0
readback_rd_A	1195514048	6701	0	0
readback_regwen_rd_A	1195514048	4037	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195514048	252083	0	0
T5	16303	0	0	0
T6	19569	1151	0	0
T11	67200	0	0	0
T14	34538	0	0	0
T15	1661	0	0	0
T16	66003	0	0	0
T18	0	8058	0	0
T24	100739	0	0	0
T25	0	6130	0	0
T26	0	4515	0	0
T29	0	7405	0	0
T30	74109	0	0	0
T31	69237	0	0	0
T32	33780	0	0	0
T47	0	3994	0	0
T62	0	2741	0	0
T65	0	895	0	0
T66	0	3373	0	0
T67	0	1559	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195514048	5960	0	0
T5	16303	0	0	0
T6	19569	92	0	0
T11	67200	0	0	0
T14	34538	0	0	0
T15	1661	0	0	0
T16	66003	0	0	0
T24	100739	0	0	0
T26	0	314	0	0
T30	74109	0	0	0
T31	69237	0	0	0
T32	33780	0	0	0
T47	0	320	0	0
T55	0	621	0	0
T56	0	408	0	0
T65	0	178	0	0
T67	0	85	0	0
T137	0	631	0	0
T138	0	68	0	0
T139	0	107	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195514048	5408	0	0
T5	16303	0	0	0
T6	19569	53	0	0
T11	67200	0	0	0
T14	34538	0	0	0
T15	1661	0	0	0
T16	66003	0	0	0
T24	100739	0	0	0
T26	0	415	0	0
T30	74109	0	0	0
T31	69237	0	0	0
T32	33780	0	0	0
T47	0	229	0	0
T55	0	573	0	0
T56	0	288	0	0
T65	0	187	0	0
T67	0	75	0	0
T137	0	624	0	0
T138	0	35	0	0
T139	0	102	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195514048	5811	0	0
T5	16303	0	0	0
T6	19569	71	0	0
T11	67200	0	0	0
T14	34538	0	0	0
T15	1661	0	0	0
T16	66003	0	0	0
T24	100739	0	0	0
T26	0	302	0	0
T30	74109	0	0	0
T31	69237	0	0	0
T32	33780	0	0	0
T47	0	265	0	0
T55	0	518	0	0
T56	0	435	0	0
T65	0	121	0	0
T67	0	52	0	0
T137	0	737	0	0
T138	0	54	0	0
T139	0	153	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195514048	6701	0	0
T5	16303	0	0	0
T6	19569	43	0	0
T11	67200	0	0	0
T14	34538	0	0	0
T15	1661	0	0	0
T16	66003	0	0	0
T24	100739	0	0	0
T26	0	374	0	0
T28	0	80	0	0
T30	74109	0	0	0
T31	69237	0	0	0
T32	33780	0	0	0
T47	0	260	0	0
T55	0	475	0	0
T56	0	363	0	0
T65	0	125	0	0
T67	0	42	0	0
T140	0	129	0	0
T141	0	72	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195514048	4037	0	0
T5	16303	0	0	0
T6	19569	29	0	0
T11	67200	0	0	0
T14	34538	0	0	0
T15	1661	0	0	0
T16	66003	0	0	0
T24	100739	0	0	0
T26	0	314	0	0
T30	74109	0	0	0
T31	69237	0	0	0
T32	33780	0	0	0
T47	0	234	0	0
T55	0	591	0	0
T56	0	298	0	0
T65	0	107	0	0
T67	0	72	0	0
T137	0	552	0	0
T138	0	42	0	0
T139	0	118	0	0