SRAM_CTRL/RET Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: 3df77bec1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.261m	476.890us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	69.319us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.670s	32.379us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.940s	299.671us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	62.793us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.950s	74.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.670s	32.379us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	62.793us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.010s	2.268ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.430s	148.517us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	31.721m	19.290ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.625m	4.262ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.331m	6.561ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	40.184m	20.413ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.840s	752.494us	50	50	100.00
V2	executable	sram_ctrl_executable	33.235m	18.478ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.493m	2.829ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.795m	92.957ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.338m	541.822us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.199m	691.612us	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.932m	76.537ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.870s	84.586us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.238h	204.365ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	0.710s	95.914us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.900s	865.486us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.900s	865.486us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	69.319us	5	5	100.00
		sram_ctrl_csr_rw	0.670s	32.379us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	62.793us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.760s	22.739us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	69.319us	5	5	100.00
		sram_ctrl_csr_rw	0.670s	32.379us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	62.793us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.760s	22.739us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	12.540s	1.132ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.850s	566.711us	5	5	100.00
		sram_ctrl_tl_intg_err	2.480s	671.535us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.850s	566.711us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.480s	671.535us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.932m	76.537ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.670s	32.379us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	33.235m	18.478ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	33.235m	18.478ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	33.235m	18.478ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.840s	752.494us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	12.540s	1.132ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.261m	476.890us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.261m	476.890us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	33.235m	18.478ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.850s	566.711us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.840s	752.494us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.850s	566.711us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.850s	566.711us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.261m	476.890us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.850s	566.711us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.967h	6.435ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1039	1040	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	16	100.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 22.sram_ctrl_stress_all_with_rand_reset.1873674154
      Line 403, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 14976513137 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xf4f72489
        UVM_INFO @ 14976513137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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