| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2881073667 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.853020333 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1563071636 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1369480569 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4157332619 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2750580753 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.732663449 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3693800355 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3890015884 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4267402157 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2027630896 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1465293291 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1667118077 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3044488618 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3155983905 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.724150745 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.478063707 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2721681494 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.41479383 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1467589674 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1492360827 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2358747969 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2905041442 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1842320778 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1838199646 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3111124887 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4104958172 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3563671810 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3320797300 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.233559125 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2079297430 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1492396107 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1279720055 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.588117322 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1841529655 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3489665022 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3517290677 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1053016516 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3372934501 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1445769686 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3301580822 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.122711152 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3430846656 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.199209876 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2132916745 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3275580081 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.34596637 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.188965902 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1345402687 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3097324376 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3272901440 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3588583226 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4184303555 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3319591246 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2140155614 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4179514547 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2237819514 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3285982075 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1126453380 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3516041765 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3500558820 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2511185655 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2298092110 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2755555679 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2573097390 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.996904741 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2053349671 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.843632044 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2188048620 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.682994005 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.849931803 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4260833301 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.344296186 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1133234432 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.929869967 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3209222737 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3054074592 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.768202568 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.774242569 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.466222767 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2569357099 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2339666879 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.552032004 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3098249552 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2267432877 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4020540336 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3002807590 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3965045500 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3885975334 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3525394529 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3273864743 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2575991886 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4071363059 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2814649755 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.616120956 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3225896320 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1409933694 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.752889488 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.25131538 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3419107741 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.167026190 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.887869265 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.418366038 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3576559533 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2670163394 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2127281005 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3960906635 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2277718349 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4077057611 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.510176596 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4065053294 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2821876493 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3945453821 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3953549014 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3523840998 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1889135640 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2905360863 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4232557417 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.864065757 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1292683960 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2572337166 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3806529561 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.26445936 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2407191177 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2287403743 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.761645298 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.97396111 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3959680165 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2731856964 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3949904850 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.508276798 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.3312381537 |
| /workspace/coverage/default/0.sram_ctrl_bijection.3209962373 |
| /workspace/coverage/default/0.sram_ctrl_executable.1036682447 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.805576970 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.3420222906 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2110771186 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.3662892301 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.1510213897 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.1106318683 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1236411293 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.4152218105 |
| /workspace/coverage/default/0.sram_ctrl_regwen.3577683930 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.1029243382 |
| /workspace/coverage/default/0.sram_ctrl_smoke.2167924605 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.3297525400 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1273160446 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1374294006 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.931255518 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.508553643 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.1826433802 |
| /workspace/coverage/default/1.sram_ctrl_bijection.2525126887 |
| /workspace/coverage/default/1.sram_ctrl_executable.2126584609 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.2641429488 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1811802462 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.13983945 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.3862151304 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.1418100226 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2269928189 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.1026669049 |
| /workspace/coverage/default/1.sram_ctrl_regwen.1821137788 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.23581301 |
| /workspace/coverage/default/1.sram_ctrl_smoke.2409007868 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.3305321511 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2259456822 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2655865679 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1931060690 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.692108529 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2366707220 |
| /workspace/coverage/default/10.sram_ctrl_bijection.2768201501 |
| /workspace/coverage/default/10.sram_ctrl_executable.1590997378 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.3169735786 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.1819487741 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3508157844 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.777398896 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.3490253717 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.3325598642 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2479411185 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.1289341333 |
| /workspace/coverage/default/10.sram_ctrl_regwen.2266342360 |
| /workspace/coverage/default/10.sram_ctrl_smoke.128613323 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.3821139947 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1383759516 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.319977819 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4180153601 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.661920 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.3663635559 |
| /workspace/coverage/default/11.sram_ctrl_bijection.3205885475 |
| /workspace/coverage/default/11.sram_ctrl_executable.2982866792 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.4166372920 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2337135508 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2315062239 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.2239141438 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.208068220 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.2052163694 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3182755397 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.4011303508 |
| /workspace/coverage/default/11.sram_ctrl_regwen.2487971216 |
| /workspace/coverage/default/11.sram_ctrl_smoke.921149576 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.1380890861 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1927653650 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.776528439 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2603941830 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1756073400 |
| /workspace/coverage/default/12.sram_ctrl_bijection.2373433529 |
| /workspace/coverage/default/12.sram_ctrl_executable.1899295603 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3488599717 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.2404056490 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.958169641 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.3273843851 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.3669717659 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.1710674849 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3409319473 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.1016240002 |
| /workspace/coverage/default/12.sram_ctrl_regwen.188518386 |
| /workspace/coverage/default/12.sram_ctrl_smoke.3313078707 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.733503902 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.353401974 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.883377248 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1892999188 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.914203221 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.563598113 |
| /workspace/coverage/default/13.sram_ctrl_bijection.3676025329 |
| /workspace/coverage/default/13.sram_ctrl_executable.2988721934 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.654796325 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1086311579 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1201170694 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.2960933184 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.2098566688 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.384566759 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1642450831 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1996748909 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2298715482 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1611504323 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.772142269 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.994067427 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.4257490847 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1428825192 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1807017941 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.4209202619 |
| /workspace/coverage/default/14.sram_ctrl_bijection.1869695359 |
| /workspace/coverage/default/14.sram_ctrl_executable.2639371741 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.3335383965 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.678205018 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1948372264 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.2816677141 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.4013752309 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.115196152 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3785599727 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.317525436 |
| /workspace/coverage/default/14.sram_ctrl_regwen.1346901542 |
| /workspace/coverage/default/14.sram_ctrl_smoke.4154492157 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.1497461376 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2483214928 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1264144191 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1125289818 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2059134064 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.3451832458 |
| /workspace/coverage/default/15.sram_ctrl_bijection.3477380061 |
| /workspace/coverage/default/15.sram_ctrl_executable.3957696348 |
| /workspace/coverage/default/15.sram_ctrl_lc_escalation.1469831098 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.4030972447 |
| /workspace/coverage/default/15.sram_ctrl_mem_partial_access.495680717 |
| /workspace/coverage/default/15.sram_ctrl_mem_walk.1157268897 |
| /workspace/coverage/default/15.sram_ctrl_multiple_keys.540416955 |
| /workspace/coverage/default/15.sram_ctrl_partial_access.3395798390 |
| /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2777172173 |
| /workspace/coverage/default/15.sram_ctrl_ram_cfg.2561499719 |
| /workspace/coverage/default/15.sram_ctrl_regwen.137733462 |
| /workspace/coverage/default/15.sram_ctrl_smoke.557844693 |
| /workspace/coverage/default/15.sram_ctrl_stress_all.3069653125 |
| /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2918432928 |
| /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1659126067 |
| /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2077408067 |
| /workspace/coverage/default/16.sram_ctrl_access_during_key_req.782157767 |
| /workspace/coverage/default/16.sram_ctrl_alert_test.973957576 |
| /workspace/coverage/default/16.sram_ctrl_bijection.1613275155 |
| /workspace/coverage/default/16.sram_ctrl_executable.2836914144 |
| /workspace/coverage/default/16.sram_ctrl_lc_escalation.660050373 |
| /workspace/coverage/default/16.sram_ctrl_max_throughput.236537578 |
| /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3225135234 |
| /workspace/coverage/default/16.sram_ctrl_mem_walk.3515549862 |
| /workspace/coverage/default/16.sram_ctrl_multiple_keys.296826080 |
| /workspace/coverage/default/16.sram_ctrl_partial_access.420474960 |
| /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1021240822 |
| /workspace/coverage/default/16.sram_ctrl_ram_cfg.1042111680 |
| /workspace/coverage/default/16.sram_ctrl_regwen.3951729318 |
| /workspace/coverage/default/16.sram_ctrl_smoke.2281060639 |
| /workspace/coverage/default/16.sram_ctrl_stress_all.696612132 |
| /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2151404964 |
| /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1931772905 |
| /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4071819307 |
| /workspace/coverage/default/17.sram_ctrl_alert_test.2772434906 |
| /workspace/coverage/default/17.sram_ctrl_bijection.2225025344 |
| /workspace/coverage/default/17.sram_ctrl_executable.201490817 |
| /workspace/coverage/default/17.sram_ctrl_lc_escalation.1052042964 |
| /workspace/coverage/default/17.sram_ctrl_max_throughput.2737049075 |
| /workspace/coverage/default/17.sram_ctrl_mem_partial_access.3307242270 |
| /workspace/coverage/default/17.sram_ctrl_mem_walk.1275106180 |
| /workspace/coverage/default/17.sram_ctrl_multiple_keys.2471818812 |
| /workspace/coverage/default/17.sram_ctrl_partial_access.776290415 |
| /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.2517972567 |
| /workspace/coverage/default/17.sram_ctrl_ram_cfg.2511932445 |
| /workspace/coverage/default/17.sram_ctrl_regwen.2347463572 |
| /workspace/coverage/default/17.sram_ctrl_smoke.172437368 |
| /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2275576030 |
| /workspace/coverage/default/17.sram_ctrl_stress_pipeline.2248278133 |
| /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.925416219 |
| /workspace/coverage/default/18.sram_ctrl_access_during_key_req.139628731 |
| /workspace/coverage/default/18.sram_ctrl_alert_test.1034297986 |
| /workspace/coverage/default/18.sram_ctrl_bijection.990645494 |
| /workspace/coverage/default/18.sram_ctrl_executable.97467037 |
| /workspace/coverage/default/18.sram_ctrl_lc_escalation.1403828254 |
| /workspace/coverage/default/18.sram_ctrl_max_throughput.1338996133 |
| /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1728221298 |
| /workspace/coverage/default/18.sram_ctrl_mem_walk.2525669763 |
| /workspace/coverage/default/18.sram_ctrl_multiple_keys.374065786 |
| /workspace/coverage/default/18.sram_ctrl_partial_access.729175203 |
| /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1075979707 |
| /workspace/coverage/default/18.sram_ctrl_ram_cfg.4214463304 |
| /workspace/coverage/default/18.sram_ctrl_regwen.3904536696 |
| /workspace/coverage/default/18.sram_ctrl_smoke.317259103 |
| /workspace/coverage/default/18.sram_ctrl_stress_all.644995246 |
| /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1553653070 |
| /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1903421938 |
| /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1095139695 |
| /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2493437140 |
| /workspace/coverage/default/19.sram_ctrl_alert_test.1365797635 |
| /workspace/coverage/default/19.sram_ctrl_bijection.259609272 |
| /workspace/coverage/default/19.sram_ctrl_executable.1527606609 |
| /workspace/coverage/default/19.sram_ctrl_lc_escalation.1206261226 |
| /workspace/coverage/default/19.sram_ctrl_max_throughput.205202513 |
| /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1280564798 |
| /workspace/coverage/default/19.sram_ctrl_mem_walk.1546796138 |
| /workspace/coverage/default/19.sram_ctrl_multiple_keys.3813260669 |
| /workspace/coverage/default/19.sram_ctrl_partial_access.1446706919 |
| /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1457511330 |
| /workspace/coverage/default/19.sram_ctrl_ram_cfg.2126481347 |
| /workspace/coverage/default/19.sram_ctrl_regwen.2559987940 |
| /workspace/coverage/default/19.sram_ctrl_smoke.3861043695 |
| /workspace/coverage/default/19.sram_ctrl_stress_all.2004215373 |
| /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1406400266 |
| /workspace/coverage/default/19.sram_ctrl_stress_pipeline.79315968 |
| /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1076408421 |
| /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2438182892 |
| /workspace/coverage/default/2.sram_ctrl_alert_test.3618183820 |
| /workspace/coverage/default/2.sram_ctrl_bijection.1208468636 |
| /workspace/coverage/default/2.sram_ctrl_executable.1623857850 |
| /workspace/coverage/default/2.sram_ctrl_lc_escalation.3183205303 |
| /workspace/coverage/default/2.sram_ctrl_max_throughput.1701491870 |
| /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2576854881 |
| /workspace/coverage/default/2.sram_ctrl_mem_walk.4191660174 |
| /workspace/coverage/default/2.sram_ctrl_multiple_keys.3180008099 |
| /workspace/coverage/default/2.sram_ctrl_partial_access.2864295150 |
| /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.3575187982 |
| /workspace/coverage/default/2.sram_ctrl_ram_cfg.526503098 |
| /workspace/coverage/default/2.sram_ctrl_regwen.778774442 |
| /workspace/coverage/default/2.sram_ctrl_sec_cm.2093182860 |
| /workspace/coverage/default/2.sram_ctrl_smoke.1152244838 |
| /workspace/coverage/default/2.sram_ctrl_stress_all.2182402021 |
| /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2552558673 |
| /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2413066733 |
| /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2057787399 |
| /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3939718875 |
| /workspace/coverage/default/20.sram_ctrl_alert_test.765675456 |
| /workspace/coverage/default/20.sram_ctrl_bijection.2007686246 |
| /workspace/coverage/default/20.sram_ctrl_executable.1831915926 |
| /workspace/coverage/default/20.sram_ctrl_lc_escalation.3846564684 |
| /workspace/coverage/default/20.sram_ctrl_max_throughput.2428122193 |
| /workspace/coverage/default/20.sram_ctrl_mem_partial_access.3604334247 |
| /workspace/coverage/default/20.sram_ctrl_mem_walk.232517742 |
| /workspace/coverage/default/20.sram_ctrl_multiple_keys.3752822432 |
| /workspace/coverage/default/20.sram_ctrl_partial_access.220985469 |
| /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2582456207 |
| /workspace/coverage/default/20.sram_ctrl_smoke.3190613300 |
| /workspace/coverage/default/20.sram_ctrl_stress_all.3489611952 |
| /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.696727926 |
| /workspace/coverage/default/20.sram_ctrl_stress_pipeline.4081247886 |
| /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3626359701 |
| /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3085033747 |
| /workspace/coverage/default/21.sram_ctrl_alert_test.464308950 |
| /workspace/coverage/default/21.sram_ctrl_bijection.1288892357 |
| /workspace/coverage/default/21.sram_ctrl_executable.2929479282 |
| /workspace/coverage/default/21.sram_ctrl_lc_escalation.1430846400 |
| /workspace/coverage/default/21.sram_ctrl_max_throughput.1032600260 |
| /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1212577512 |
| /workspace/coverage/default/21.sram_ctrl_mem_walk.1475581293 |
| /workspace/coverage/default/21.sram_ctrl_multiple_keys.3463557720 |
| /workspace/coverage/default/21.sram_ctrl_partial_access.2170267661 |
| /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2202333340 |
| /workspace/coverage/default/21.sram_ctrl_ram_cfg.3348124142 |
| /workspace/coverage/default/21.sram_ctrl_regwen.3120161595 |
| /workspace/coverage/default/21.sram_ctrl_smoke.945692317 |
| /workspace/coverage/default/21.sram_ctrl_stress_all.3297372477 |
| /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2833261632 |
| /workspace/coverage/default/21.sram_ctrl_stress_pipeline.1063902004 |
| /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3974441216 |
| /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2402185413 |
| /workspace/coverage/default/22.sram_ctrl_alert_test.3884030747 |
| /workspace/coverage/default/22.sram_ctrl_bijection.1395462140 |
| /workspace/coverage/default/22.sram_ctrl_executable.465599208 |
| /workspace/coverage/default/22.sram_ctrl_lc_escalation.914736418 |
| /workspace/coverage/default/22.sram_ctrl_max_throughput.3999033514 |
| /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2139969968 |
| /workspace/coverage/default/22.sram_ctrl_mem_walk.3003824292 |
| /workspace/coverage/default/22.sram_ctrl_multiple_keys.461963141 |
| /workspace/coverage/default/22.sram_ctrl_partial_access.3073648771 |
| /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2065011042 |
| /workspace/coverage/default/22.sram_ctrl_ram_cfg.4170203724 |
| /workspace/coverage/default/22.sram_ctrl_regwen.2217459287 |
| /workspace/coverage/default/22.sram_ctrl_smoke.1927810120 |
| /workspace/coverage/default/22.sram_ctrl_stress_all.1012656987 |
| /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1032783035 |
| /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2077262046 |
| /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.4288060399 |
| /workspace/coverage/default/23.sram_ctrl_access_during_key_req.1183477320 |
| /workspace/coverage/default/23.sram_ctrl_alert_test.2175271492 |
| /workspace/coverage/default/23.sram_ctrl_bijection.369709145 |
| /workspace/coverage/default/23.sram_ctrl_executable.2987770144 |
| /workspace/coverage/default/23.sram_ctrl_lc_escalation.2667735661 |
| /workspace/coverage/default/23.sram_ctrl_max_throughput.1466454909 |
| /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2711040997 |
| /workspace/coverage/default/23.sram_ctrl_mem_walk.3991426890 |
| /workspace/coverage/default/23.sram_ctrl_multiple_keys.3837293727 |
| /workspace/coverage/default/23.sram_ctrl_partial_access.4071263280 |
| /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.228270370 |
| /workspace/coverage/default/23.sram_ctrl_ram_cfg.3969187987 |
| /workspace/coverage/default/23.sram_ctrl_regwen.1562863835 |
| /workspace/coverage/default/23.sram_ctrl_smoke.2145504592 |
| /workspace/coverage/default/23.sram_ctrl_stress_all.2560751084 |
| /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2965760432 |
| /workspace/coverage/default/23.sram_ctrl_stress_pipeline.90581857 |
| /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1302670690 |
| /workspace/coverage/default/24.sram_ctrl_access_during_key_req.1250483590 |
| /workspace/coverage/default/24.sram_ctrl_alert_test.2265536026 |
| /workspace/coverage/default/24.sram_ctrl_bijection.4284307726 |
| /workspace/coverage/default/24.sram_ctrl_executable.1051063245 |
| /workspace/coverage/default/24.sram_ctrl_lc_escalation.3741993177 |
| /workspace/coverage/default/24.sram_ctrl_max_throughput.947000252 |
| /workspace/coverage/default/24.sram_ctrl_mem_partial_access.4169586448 |
| /workspace/coverage/default/24.sram_ctrl_mem_walk.1228639928 |
| /workspace/coverage/default/24.sram_ctrl_multiple_keys.1350631970 |
| /workspace/coverage/default/24.sram_ctrl_partial_access.1717137718 |
| /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2244601987 |
| /workspace/coverage/default/24.sram_ctrl_ram_cfg.627311474 |
| /workspace/coverage/default/24.sram_ctrl_regwen.1072272863 |
| /workspace/coverage/default/24.sram_ctrl_smoke.1995251071 |
| /workspace/coverage/default/24.sram_ctrl_stress_all.2364196798 |
| /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1259014575 |
| /workspace/coverage/default/24.sram_ctrl_stress_pipeline.322676652 |
| /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1785488417 |
| /workspace/coverage/default/25.sram_ctrl_access_during_key_req.3977238416 |
| /workspace/coverage/default/25.sram_ctrl_alert_test.2051422316 |
| /workspace/coverage/default/25.sram_ctrl_bijection.2694183140 |
| /workspace/coverage/default/25.sram_ctrl_executable.961316430 |
| /workspace/coverage/default/25.sram_ctrl_lc_escalation.1424843481 |
| /workspace/coverage/default/25.sram_ctrl_max_throughput.2704010607 |
| /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2303595088 |
| /workspace/coverage/default/25.sram_ctrl_mem_walk.1261881186 |
| /workspace/coverage/default/25.sram_ctrl_multiple_keys.2771733630 |
| /workspace/coverage/default/25.sram_ctrl_partial_access.2227993045 |
| /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2538494377 |
| /workspace/coverage/default/25.sram_ctrl_ram_cfg.3898527127 |
| /workspace/coverage/default/25.sram_ctrl_regwen.3525952333 |
| /workspace/coverage/default/25.sram_ctrl_smoke.3161706403 |
| /workspace/coverage/default/25.sram_ctrl_stress_all.4182619583 |
| /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1748082013 |
| /workspace/coverage/default/25.sram_ctrl_stress_pipeline.1627660134 |
| /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2260038057 |
| /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1201286265 |
| /workspace/coverage/default/26.sram_ctrl_alert_test.3901004259 |
| /workspace/coverage/default/26.sram_ctrl_bijection.2170667597 |
| /workspace/coverage/default/26.sram_ctrl_executable.616346158 |
| /workspace/coverage/default/26.sram_ctrl_lc_escalation.1440843817 |
| /workspace/coverage/default/26.sram_ctrl_max_throughput.859918062 |
| /workspace/coverage/default/26.sram_ctrl_mem_partial_access.229092767 |
| /workspace/coverage/default/26.sram_ctrl_mem_walk.31916911 |
| /workspace/coverage/default/26.sram_ctrl_multiple_keys.1167374299 |
| /workspace/coverage/default/26.sram_ctrl_partial_access.793182557 |
| /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2504371435 |
| /workspace/coverage/default/26.sram_ctrl_ram_cfg.2910672717 |
| /workspace/coverage/default/26.sram_ctrl_regwen.1738226570 |
| /workspace/coverage/default/26.sram_ctrl_smoke.1566826694 |
| /workspace/coverage/default/26.sram_ctrl_stress_all.1301022357 |
| /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2060547251 |
| /workspace/coverage/default/26.sram_ctrl_stress_pipeline.341619119 |
| /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4291137891 |
| /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1801317939 |
| /workspace/coverage/default/27.sram_ctrl_alert_test.1087658172 |
| /workspace/coverage/default/27.sram_ctrl_bijection.1232603672 |
| /workspace/coverage/default/27.sram_ctrl_executable.1504603010 |
| /workspace/coverage/default/27.sram_ctrl_lc_escalation.2876804259 |
| /workspace/coverage/default/27.sram_ctrl_max_throughput.3845212357 |
| /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3111170002 |
| /workspace/coverage/default/27.sram_ctrl_mem_walk.1476202655 |
| /workspace/coverage/default/27.sram_ctrl_multiple_keys.2497114993 |
| /workspace/coverage/default/27.sram_ctrl_partial_access.374939176 |
| /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.4102467 |
| /workspace/coverage/default/27.sram_ctrl_ram_cfg.401792799 |
| /workspace/coverage/default/27.sram_ctrl_regwen.3948954121 |
| /workspace/coverage/default/27.sram_ctrl_smoke.2982572184 |
| /workspace/coverage/default/27.sram_ctrl_stress_all.71737847 |
| /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1863566329 |
| /workspace/coverage/default/27.sram_ctrl_stress_pipeline.3774509420 |
| /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.4217973932 |
| /workspace/coverage/default/28.sram_ctrl_access_during_key_req.2037897597 |
| /workspace/coverage/default/28.sram_ctrl_alert_test.1059878897 |
| /workspace/coverage/default/28.sram_ctrl_bijection.4152212159 |
| /workspace/coverage/default/28.sram_ctrl_executable.2156422220 |
| /workspace/coverage/default/28.sram_ctrl_lc_escalation.4006904434 |
| /workspace/coverage/default/28.sram_ctrl_max_throughput.488196455 |
| /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4085278182 |
| /workspace/coverage/default/28.sram_ctrl_mem_walk.2321881104 |
| /workspace/coverage/default/28.sram_ctrl_multiple_keys.1873072707 |
| /workspace/coverage/default/28.sram_ctrl_partial_access.2518840725 |
| /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1553326027 |
| /workspace/coverage/default/28.sram_ctrl_ram_cfg.3495224094 |
| /workspace/coverage/default/28.sram_ctrl_regwen.2953958815 |
| /workspace/coverage/default/28.sram_ctrl_smoke.2402844545 |
| /workspace/coverage/default/28.sram_ctrl_stress_all.88739420 |
| /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3673396956 |
| /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3760465822 |
| /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2382831493 |
| /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3483020219 |
| /workspace/coverage/default/29.sram_ctrl_alert_test.2693253476 |
| /workspace/coverage/default/29.sram_ctrl_bijection.2622509599 |
| /workspace/coverage/default/29.sram_ctrl_executable.1758155773 |
| /workspace/coverage/default/29.sram_ctrl_lc_escalation.3893942058 |
| /workspace/coverage/default/29.sram_ctrl_max_throughput.316611957 |
| /workspace/coverage/default/29.sram_ctrl_mem_partial_access.4279411916 |
| /workspace/coverage/default/29.sram_ctrl_mem_walk.2820242736 |
| /workspace/coverage/default/29.sram_ctrl_multiple_keys.1210182069 |
| /workspace/coverage/default/29.sram_ctrl_partial_access.639844336 |
| /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.1482749622 |
| /workspace/coverage/default/29.sram_ctrl_ram_cfg.842865410 |
| /workspace/coverage/default/29.sram_ctrl_regwen.2404973035 |
| /workspace/coverage/default/29.sram_ctrl_smoke.443432634 |
| /workspace/coverage/default/29.sram_ctrl_stress_all.3578296660 |
| /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1956373523 |
| /workspace/coverage/default/29.sram_ctrl_stress_pipeline.447222885 |
| /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2655856756 |
| /workspace/coverage/default/3.sram_ctrl_access_during_key_req.4074989641 |
| /workspace/coverage/default/3.sram_ctrl_alert_test.2741379541 |
| /workspace/coverage/default/3.sram_ctrl_bijection.123437299 |
| /workspace/coverage/default/3.sram_ctrl_executable.1670546204 |
| /workspace/coverage/default/3.sram_ctrl_lc_escalation.1222703654 |
| /workspace/coverage/default/3.sram_ctrl_max_throughput.606852680 |
| /workspace/coverage/default/3.sram_ctrl_mem_partial_access.2072036472 |
| /workspace/coverage/default/3.sram_ctrl_mem_walk.1484225226 |
| /workspace/coverage/default/3.sram_ctrl_multiple_keys.1493508826 |
| /workspace/coverage/default/3.sram_ctrl_partial_access.2546767231 |
| /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.777763753 |
| /workspace/coverage/default/3.sram_ctrl_ram_cfg.2555494757 |
| /workspace/coverage/default/3.sram_ctrl_regwen.3730185878 |
| /workspace/coverage/default/3.sram_ctrl_sec_cm.76396430 |
| /workspace/coverage/default/3.sram_ctrl_smoke.935026006 |
| /workspace/coverage/default/3.sram_ctrl_stress_all.1318065015 |
| /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2544003901 |
| /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2506699711 |
| /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3096650875 |
| /workspace/coverage/default/30.sram_ctrl_access_during_key_req.1629299865 |
| /workspace/coverage/default/30.sram_ctrl_alert_test.1881264484 |
| /workspace/coverage/default/30.sram_ctrl_bijection.3121157547 |
| /workspace/coverage/default/30.sram_ctrl_executable.1332244428 |
| /workspace/coverage/default/30.sram_ctrl_lc_escalation.1151011590 |
| /workspace/coverage/default/30.sram_ctrl_max_throughput.2335952373 |
| /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2712832213 |
| /workspace/coverage/default/30.sram_ctrl_mem_walk.1202432124 |
| /workspace/coverage/default/30.sram_ctrl_multiple_keys.2608072769 |
| /workspace/coverage/default/30.sram_ctrl_partial_access.3699349984 |
| /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.1115444750 |
| /workspace/coverage/default/30.sram_ctrl_ram_cfg.3583071594 |
| /workspace/coverage/default/30.sram_ctrl_regwen.3065375126 |
| /workspace/coverage/default/30.sram_ctrl_smoke.1824004401 |
| /workspace/coverage/default/30.sram_ctrl_stress_all.2913947972 |
| /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3710246556 |
| /workspace/coverage/default/30.sram_ctrl_stress_pipeline.2018444287 |
| /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.744341464 |
| /workspace/coverage/default/31.sram_ctrl_access_during_key_req.2175867605 |
| /workspace/coverage/default/31.sram_ctrl_alert_test.1291919792 |
| /workspace/coverage/default/31.sram_ctrl_bijection.1691202888 |
| /workspace/coverage/default/31.sram_ctrl_executable.3152468965 |
| /workspace/coverage/default/31.sram_ctrl_lc_escalation.3422069565 |
| /workspace/coverage/default/31.sram_ctrl_max_throughput.2102420658 |
| /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2864684672 |
| /workspace/coverage/default/31.sram_ctrl_mem_walk.471307452 |
| /workspace/coverage/default/31.sram_ctrl_multiple_keys.1716826161 |
| /workspace/coverage/default/31.sram_ctrl_partial_access.4236666314 |
| /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2892519899 |
| /workspace/coverage/default/31.sram_ctrl_ram_cfg.607296734 |
| /workspace/coverage/default/31.sram_ctrl_regwen.4165371630 |
| /workspace/coverage/default/31.sram_ctrl_smoke.2959099731 |
| /workspace/coverage/default/31.sram_ctrl_stress_all.991134126 |
| /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1557221164 |
| /workspace/coverage/default/31.sram_ctrl_stress_pipeline.46097027 |
| /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2052999653 |
| /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2081531154 |
| /workspace/coverage/default/32.sram_ctrl_alert_test.1372148985 |
| /workspace/coverage/default/32.sram_ctrl_bijection.775995541 |
| /workspace/coverage/default/32.sram_ctrl_executable.910026315 |
| /workspace/coverage/default/32.sram_ctrl_lc_escalation.2664407782 |
| /workspace/coverage/default/32.sram_ctrl_max_throughput.2271813352 |
| /workspace/coverage/default/32.sram_ctrl_mem_partial_access.882638933 |
| /workspace/coverage/default/32.sram_ctrl_mem_walk.882376494 |
| /workspace/coverage/default/32.sram_ctrl_multiple_keys.1870248199 |
| /workspace/coverage/default/32.sram_ctrl_partial_access.440011586 |
| /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2973237347 |
| /workspace/coverage/default/32.sram_ctrl_ram_cfg.2940591471 |
| /workspace/coverage/default/32.sram_ctrl_regwen.2076817879 |
| /workspace/coverage/default/32.sram_ctrl_smoke.2377428049 |
| /workspace/coverage/default/32.sram_ctrl_stress_all.856122638 |
| /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3192546268 |
| /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1990456673 |
| /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1921932207 |
| /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1807988451 |
| /workspace/coverage/default/33.sram_ctrl_alert_test.317013723 |
| /workspace/coverage/default/33.sram_ctrl_bijection.566389689 |
| /workspace/coverage/default/33.sram_ctrl_executable.2838872204 |
| /workspace/coverage/default/33.sram_ctrl_lc_escalation.4132701773 |
| /workspace/coverage/default/33.sram_ctrl_max_throughput.2575189511 |
| /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2229778096 |
| /workspace/coverage/default/33.sram_ctrl_mem_walk.3215917348 |
| /workspace/coverage/default/33.sram_ctrl_multiple_keys.1999434439 |
| /workspace/coverage/default/33.sram_ctrl_partial_access.42369876 |
| /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1808684719 |
| /workspace/coverage/default/33.sram_ctrl_ram_cfg.3362615564 |
| /workspace/coverage/default/33.sram_ctrl_regwen.2070569529 |
| /workspace/coverage/default/33.sram_ctrl_smoke.3287689487 |
| /workspace/coverage/default/33.sram_ctrl_stress_all.3597262956 |
| /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.668295507 |
| /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2736827633 |
| /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3985605639 |
| /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2267223703 |
| /workspace/coverage/default/34.sram_ctrl_alert_test.2582059516 |
| /workspace/coverage/default/34.sram_ctrl_bijection.703682689 |
| /workspace/coverage/default/34.sram_ctrl_executable.3784786593 |
| /workspace/coverage/default/34.sram_ctrl_lc_escalation.3201113563 |
| /workspace/coverage/default/34.sram_ctrl_max_throughput.2512767483 |
| /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2295394487 |
| /workspace/coverage/default/34.sram_ctrl_mem_walk.237347529 |
| /workspace/coverage/default/34.sram_ctrl_multiple_keys.3889309614 |
| /workspace/coverage/default/34.sram_ctrl_partial_access.2643668655 |
| /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1398410619 |
| /workspace/coverage/default/34.sram_ctrl_ram_cfg.1891600425 |
| /workspace/coverage/default/34.sram_ctrl_regwen.3802795735 |
| /workspace/coverage/default/34.sram_ctrl_smoke.3600775213 |
| /workspace/coverage/default/34.sram_ctrl_stress_all.3948105446 |
| /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3099010166 |
| /workspace/coverage/default/34.sram_ctrl_stress_pipeline.295843099 |
| /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1253460603 |
| /workspace/coverage/default/35.sram_ctrl_access_during_key_req.4085379511 |
| /workspace/coverage/default/35.sram_ctrl_alert_test.4232043531 |
| /workspace/coverage/default/35.sram_ctrl_bijection.3545526256 |
| /workspace/coverage/default/35.sram_ctrl_executable.3932155128 |
| /workspace/coverage/default/35.sram_ctrl_lc_escalation.10958769 |
| /workspace/coverage/default/35.sram_ctrl_max_throughput.454364006 |
| /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2926729529 |
| /workspace/coverage/default/35.sram_ctrl_mem_walk.671900996 |
| /workspace/coverage/default/35.sram_ctrl_multiple_keys.2940070663 |
| /workspace/coverage/default/35.sram_ctrl_partial_access.1202279501 |
| /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3828361776 |
| /workspace/coverage/default/35.sram_ctrl_ram_cfg.3312289404 |
| /workspace/coverage/default/35.sram_ctrl_regwen.765372831 |
| /workspace/coverage/default/35.sram_ctrl_smoke.4046067833 |
| /workspace/coverage/default/35.sram_ctrl_stress_all.671814750 |
| /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4173725383 |
| /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2667056866 |
| /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1389952069 |
| /workspace/coverage/default/36.sram_ctrl_access_during_key_req.1873999452 |
| /workspace/coverage/default/36.sram_ctrl_alert_test.1661501091 |
| /workspace/coverage/default/36.sram_ctrl_bijection.1477868041 |
| /workspace/coverage/default/36.sram_ctrl_executable.1019979559 |
| /workspace/coverage/default/36.sram_ctrl_lc_escalation.4094987592 |
| /workspace/coverage/default/36.sram_ctrl_max_throughput.2947971752 |
| /workspace/coverage/default/36.sram_ctrl_mem_partial_access.857066260 |
| /workspace/coverage/default/36.sram_ctrl_mem_walk.738248348 |
| /workspace/coverage/default/36.sram_ctrl_multiple_keys.1502146066 |
| /workspace/coverage/default/36.sram_ctrl_partial_access.465490384 |
| /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3268490930 |
| /workspace/coverage/default/36.sram_ctrl_ram_cfg.1580730709 |
| /workspace/coverage/default/36.sram_ctrl_regwen.4294282932 |
| /workspace/coverage/default/36.sram_ctrl_smoke.4084291694 |
| /workspace/coverage/default/36.sram_ctrl_stress_all.2099461440 |
| /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1749697684 |
| /workspace/coverage/default/36.sram_ctrl_stress_pipeline.1613295523 |
| /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.270358608 |
| /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1899700062 |
| /workspace/coverage/default/37.sram_ctrl_alert_test.1380715960 |
| /workspace/coverage/default/37.sram_ctrl_bijection.1481462933 |
| /workspace/coverage/default/37.sram_ctrl_executable.3705601011 |
| /workspace/coverage/default/37.sram_ctrl_lc_escalation.692394441 |
| /workspace/coverage/default/37.sram_ctrl_max_throughput.1302228013 |
| /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1199817487 |
| /workspace/coverage/default/37.sram_ctrl_mem_walk.1285737236 |
| /workspace/coverage/default/37.sram_ctrl_multiple_keys.4228330754 |
| /workspace/coverage/default/37.sram_ctrl_partial_access.15210461 |
| /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1736272330 |
| /workspace/coverage/default/37.sram_ctrl_ram_cfg.2852743193 |
| /workspace/coverage/default/37.sram_ctrl_regwen.1806922300 |
| /workspace/coverage/default/37.sram_ctrl_smoke.3435707976 |
| /workspace/coverage/default/37.sram_ctrl_stress_all.1641960371 |
| /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2558743177 |
| /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1782285823 |
| /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1894628601 |
| /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3391825044 |
| /workspace/coverage/default/38.sram_ctrl_alert_test.4074506524 |
| /workspace/coverage/default/38.sram_ctrl_bijection.3789041210 |
| /workspace/coverage/default/38.sram_ctrl_executable.2254586673 |
| /workspace/coverage/default/38.sram_ctrl_lc_escalation.3564801887 |
| /workspace/coverage/default/38.sram_ctrl_max_throughput.3594968369 |
| /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3477317068 |
| /workspace/coverage/default/38.sram_ctrl_mem_walk.3715866606 |
| /workspace/coverage/default/38.sram_ctrl_multiple_keys.2798718041 |
| /workspace/coverage/default/38.sram_ctrl_partial_access.504746124 |
| /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.911923392 |
| /workspace/coverage/default/38.sram_ctrl_ram_cfg.3528134900 |
| /workspace/coverage/default/38.sram_ctrl_regwen.3328945814 |
| /workspace/coverage/default/38.sram_ctrl_smoke.924512195 |
| /workspace/coverage/default/38.sram_ctrl_stress_all.1147338743 |
| /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3905743805 |
| /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2954599168 |
| /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3063212569 |
| /workspace/coverage/default/39.sram_ctrl_access_during_key_req.971046792 |
| /workspace/coverage/default/39.sram_ctrl_alert_test.2351182781 |
| /workspace/coverage/default/39.sram_ctrl_bijection.2674368738 |
| /workspace/coverage/default/39.sram_ctrl_executable.3340306182 |
| /workspace/coverage/default/39.sram_ctrl_lc_escalation.1120907702 |
| /workspace/coverage/default/39.sram_ctrl_max_throughput.784840026 |
| /workspace/coverage/default/39.sram_ctrl_mem_partial_access.253138103 |
| /workspace/coverage/default/39.sram_ctrl_mem_walk.98433770 |
| /workspace/coverage/default/39.sram_ctrl_multiple_keys.3638955466 |
| /workspace/coverage/default/39.sram_ctrl_partial_access.3321725418 |
| /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1013584500 |
| /workspace/coverage/default/39.sram_ctrl_ram_cfg.981013112 |
| /workspace/coverage/default/39.sram_ctrl_regwen.2167513487 |
| /workspace/coverage/default/39.sram_ctrl_smoke.2879764063 |
| /workspace/coverage/default/39.sram_ctrl_stress_all.3513165439 |
| /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3894109666 |
| /workspace/coverage/default/39.sram_ctrl_stress_pipeline.1693868350 |
| /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2682272235 |
| /workspace/coverage/default/4.sram_ctrl_access_during_key_req.4148790373 |
| /workspace/coverage/default/4.sram_ctrl_alert_test.2453289339 |
| /workspace/coverage/default/4.sram_ctrl_bijection.1276237681 |
| /workspace/coverage/default/4.sram_ctrl_executable.4111638948 |
| /workspace/coverage/default/4.sram_ctrl_lc_escalation.495073258 |
| /workspace/coverage/default/4.sram_ctrl_max_throughput.737402637 |
| /workspace/coverage/default/4.sram_ctrl_mem_partial_access.2364751683 |
| /workspace/coverage/default/4.sram_ctrl_mem_walk.1838492980 |
| /workspace/coverage/default/4.sram_ctrl_multiple_keys.3472989913 |
| /workspace/coverage/default/4.sram_ctrl_partial_access.2704437708 |
| /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.324857118 |
| /workspace/coverage/default/4.sram_ctrl_ram_cfg.2777789685 |
| /workspace/coverage/default/4.sram_ctrl_regwen.1495154279 |
| /workspace/coverage/default/4.sram_ctrl_smoke.996305562 |
| /workspace/coverage/default/4.sram_ctrl_stress_all.1924062316 |
| /workspace/coverage/default/4.sram_ctrl_stress_pipeline.544556365 |
| /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3065438029 |
| /workspace/coverage/default/40.sram_ctrl_access_during_key_req.2012754612 |
| /workspace/coverage/default/40.sram_ctrl_alert_test.3379738691 |
| /workspace/coverage/default/40.sram_ctrl_bijection.258075540 |
| /workspace/coverage/default/40.sram_ctrl_executable.1397063345 |
| /workspace/coverage/default/40.sram_ctrl_lc_escalation.1883656715 |
| /workspace/coverage/default/40.sram_ctrl_max_throughput.591368218 |
| /workspace/coverage/default/40.sram_ctrl_mem_partial_access.19730294 |
| /workspace/coverage/default/40.sram_ctrl_mem_walk.491785443 |
| /workspace/coverage/default/40.sram_ctrl_multiple_keys.1085671838 |
| /workspace/coverage/default/40.sram_ctrl_partial_access.848469941 |
| /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.667863079 |
| /workspace/coverage/default/40.sram_ctrl_ram_cfg.2173075761 |
| /workspace/coverage/default/40.sram_ctrl_regwen.692207100 |
| /workspace/coverage/default/40.sram_ctrl_smoke.365407700 |
| /workspace/coverage/default/40.sram_ctrl_stress_all.3889811821 |
| /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.984087561 |
| /workspace/coverage/default/40.sram_ctrl_stress_pipeline.3844363427 |
| /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.4010206951 |
| /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3596915490 |
| /workspace/coverage/default/41.sram_ctrl_alert_test.2309900294 |
| /workspace/coverage/default/41.sram_ctrl_bijection.3481846859 |
| /workspace/coverage/default/41.sram_ctrl_executable.106503415 |
| /workspace/coverage/default/41.sram_ctrl_lc_escalation.2117978566 |
| /workspace/coverage/default/41.sram_ctrl_max_throughput.3058609700 |
| /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2103270605 |
| /workspace/coverage/default/41.sram_ctrl_mem_walk.579125028 |
| /workspace/coverage/default/41.sram_ctrl_multiple_keys.981662546 |
| /workspace/coverage/default/41.sram_ctrl_partial_access.321399685 |
| /workspace/coverage/default/41.sram_ctrl_ram_cfg.4239048886 |
| /workspace/coverage/default/41.sram_ctrl_regwen.2482286241 |
| /workspace/coverage/default/41.sram_ctrl_smoke.1438169605 |
| /workspace/coverage/default/41.sram_ctrl_stress_all.1284057242 |
| /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3509626159 |
| /workspace/coverage/default/41.sram_ctrl_stress_pipeline.1230465350 |
| /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2501548600 |
| /workspace/coverage/default/42.sram_ctrl_access_during_key_req.418395344 |
| /workspace/coverage/default/42.sram_ctrl_alert_test.3431829526 |
| /workspace/coverage/default/42.sram_ctrl_bijection.441747181 |
| /workspace/coverage/default/42.sram_ctrl_executable.3003088293 |
| /workspace/coverage/default/42.sram_ctrl_lc_escalation.1879093686 |
| /workspace/coverage/default/42.sram_ctrl_max_throughput.1553268256 |
| /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1017100024 |
| /workspace/coverage/default/42.sram_ctrl_mem_walk.348234160 |
| /workspace/coverage/default/42.sram_ctrl_multiple_keys.2213857822 |
| /workspace/coverage/default/42.sram_ctrl_partial_access.3553947203 |
| /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3289404432 |
| /workspace/coverage/default/42.sram_ctrl_ram_cfg.1291079131 |
| /workspace/coverage/default/42.sram_ctrl_regwen.3442891610 |
| /workspace/coverage/default/42.sram_ctrl_smoke.3436042013 |
| /workspace/coverage/default/42.sram_ctrl_stress_all.2266654814 |
| /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3216630690 |
| /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3879275942 |
| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1179110762 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.435805069 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.1808315781 |
| /workspace/coverage/default/43.sram_ctrl_bijection.2813109933 |
| /workspace/coverage/default/43.sram_ctrl_executable.1130219139 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.526515694 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.110919614 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2413036255 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.2670106245 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.1413340388 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.1984745272 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2650869952 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.2172716454 |
| /workspace/coverage/default/43.sram_ctrl_regwen.1762519238 |
| /workspace/coverage/default/43.sram_ctrl_smoke.2518507396 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.1097847623 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1591005022 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.149429797 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3816570723 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2433110282 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.1716623437 |
| /workspace/coverage/default/44.sram_ctrl_bijection.259699809 |
| /workspace/coverage/default/44.sram_ctrl_executable.1042531043 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.3659185928 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.773533193 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2113273796 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.2715722309 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.4088995542 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.97106842 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1008080807 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.3798726950 |
| /workspace/coverage/default/44.sram_ctrl_regwen.435021392 |
| /workspace/coverage/default/44.sram_ctrl_smoke.3140504291 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.4152176904 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.186548318 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2681672199 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.333181869 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1523118557 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1768765374 |
| /workspace/coverage/default/45.sram_ctrl_bijection.1822973739 |
| /workspace/coverage/default/45.sram_ctrl_executable.968023881 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.2475099232 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.2884033900 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.201775284 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.1995803233 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.2149906203 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.1890882939 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2503823836 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.2728702117 |
| /workspace/coverage/default/45.sram_ctrl_regwen.2746043543 |
| /workspace/coverage/default/45.sram_ctrl_smoke.1646445785 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.1289807259 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2235096205 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2074321191 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1003391946 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2755338406 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.132536931 |
| /workspace/coverage/default/46.sram_ctrl_bijection.2490998998 |
| /workspace/coverage/default/46.sram_ctrl_executable.35421321 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.3017289474 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.106335773 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1064667746 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.4218122488 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.1428236484 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.711601823 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1347917823 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.2837376768 |
| /workspace/coverage/default/46.sram_ctrl_regwen.3389000215 |
| /workspace/coverage/default/46.sram_ctrl_smoke.3123835821 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.3869837378 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.61042485 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1856134325 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3652887104 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.832136061 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.2027137828 |
| /workspace/coverage/default/47.sram_ctrl_bijection.2494844729 |
| /workspace/coverage/default/47.sram_ctrl_executable.1872582317 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.990313212 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.2667410457 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3091044016 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.1155266264 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.874205911 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.3045052540 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3296888349 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3507115837 |
| /workspace/coverage/default/47.sram_ctrl_regwen.1550560975 |
| /workspace/coverage/default/47.sram_ctrl_smoke.6961222 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.1924812463 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2177298102 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.783008447 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1225861283 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.701551737 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.1116920598 |
| /workspace/coverage/default/48.sram_ctrl_bijection.1728384231 |
| /workspace/coverage/default/48.sram_ctrl_executable.2932704750 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.3670997237 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.2928472620 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4123435140 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.2728980305 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.1266844421 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.3804117540 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1839722589 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.3896245322 |
| /workspace/coverage/default/48.sram_ctrl_regwen.2721673282 |
| /workspace/coverage/default/48.sram_ctrl_smoke.3712794348 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1421174642 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.706685309 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.4112735534 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4206573962 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.100010688 |
| /workspace/coverage/default/49.sram_ctrl_bijection.3103818024 |
| /workspace/coverage/default/49.sram_ctrl_executable.2161315144 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.4111048921 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.3232931836 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3579157767 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.254737235 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.3880788030 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.718573359 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3462831821 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.3857805232 |
| /workspace/coverage/default/49.sram_ctrl_regwen.242446124 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3619504032 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1175582853 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.4087017111 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.161165153 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3343856344 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.2823125194 |
| /workspace/coverage/default/5.sram_ctrl_bijection.742695743 |
| /workspace/coverage/default/5.sram_ctrl_executable.1821084857 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.3586010697 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.69854194 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.827382545 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.868117247 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.852595799 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1716081124 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1212828980 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1281382445 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3626618462 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2763648352 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.894289317 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.202675936 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2823901546 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.409121492 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.307438873 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.288220074 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1268883817 |
| /workspace/coverage/default/6.sram_ctrl_executable.3528068234 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.3493487177 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.196879987 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.4053813242 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.495603582 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3106426437 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.2669103373 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.819614860 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.29710544 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3090475245 |
| /workspace/coverage/default/6.sram_ctrl_smoke.3118127948 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.856551905 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.3318905197 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3504801740 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1512207731 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.594123948 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1357947838 |
| /workspace/coverage/default/7.sram_ctrl_executable.109879066 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.770568428 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.708301541 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2386167037 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3426152296 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.663770040 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.1883250494 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4040726799 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.3710366854 |
| /workspace/coverage/default/7.sram_ctrl_regwen.3532129131 |
| /workspace/coverage/default/7.sram_ctrl_smoke.2635351287 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.3861859456 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1043993327 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3337970320 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3783165556 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2906856964 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.814485735 |
| /workspace/coverage/default/8.sram_ctrl_bijection.521371209 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.3696204875 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.1436341007 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2796557880 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1126591130 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.4118085843 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.2217548911 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.326216838 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.4292912259 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1595671509 |
| /workspace/coverage/default/8.sram_ctrl_smoke.1508796249 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.3342190748 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1222145713 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.507886834 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3044964100 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.4172369474 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1956814367 |
| /workspace/coverage/default/9.sram_ctrl_bijection.152321285 |
| /workspace/coverage/default/9.sram_ctrl_executable.2264571261 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3417901084 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.3313074669 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4219220408 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3139122506 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.4152483681 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.950055261 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3754417642 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2496644956 |
| /workspace/coverage/default/9.sram_ctrl_regwen.558151273 |
| /workspace/coverage/default/9.sram_ctrl_smoke.3131010326 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3771575426 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2100958917 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1588421918 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1302355196 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/46.sram_ctrl_bijection.2490998998 |
|
|
May 28 03:31:55 AM PDT 23 |
May 28 03:32:46 AM PDT 23 |
4866824960 ps |
| T2 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.35734229 |
|
|
May 28 03:21:22 AM PDT 23 |
May 28 04:05:32 AM PDT 23 |
958727669 ps |
| T3 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.1870248199 |
|
|
May 28 03:27:09 AM PDT 23 |
May 28 03:50:01 AM PDT 23 |
21660909394 ps |
| T4 |
/workspace/coverage/default/44.sram_ctrl_stress_all.4152176904 |
|
|
May 28 03:31:58 AM PDT 23 |
May 28 03:59:12 AM PDT 23 |
12719549798 ps |
| T9 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.322676652 |
|
|
May 28 03:25:06 AM PDT 23 |
May 28 03:28:43 AM PDT 23 |
28833563077 ps |
| T10 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.13983945 |
|
|
May 28 03:21:38 AM PDT 23 |
May 28 03:21:43 AM PDT 23 |
293667311 ps |
| T11 |
/workspace/coverage/default/4.sram_ctrl_alert_test.2453289339 |
|
|
May 28 03:21:26 AM PDT 23 |
May 28 03:21:27 AM PDT 23 |
14284961 ps |
| T12 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4292912259 |
|
|
May 28 03:22:25 AM PDT 23 |
May 28 03:22:26 AM PDT 23 |
85163935 ps |
| T5 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3017289474 |
|
|
May 28 03:31:55 AM PDT 23 |
May 28 03:32:02 AM PDT 23 |
513855837 ps |
| T6 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3513165439 |
|
|
May 28 03:30:30 AM PDT 23 |
May 28 04:38:20 AM PDT 23 |
31749315156 ps |
| T16 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.701551737 |
|
|
May 28 03:32:37 AM PDT 23 |
May 28 03:36:15 AM PDT 23 |
836700295 ps |
| T13 |
/workspace/coverage/default/20.sram_ctrl_regwen.2830855640 |
|
|
May 28 03:24:12 AM PDT 23 |
May 28 03:24:44 AM PDT 23 |
9005632288 ps |
| T14 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1509209132 |
|
|
May 28 03:30:21 AM PDT 23 |
May 28 03:36:57 AM PDT 23 |
16258422177 ps |
| T53 |
/workspace/coverage/default/30.sram_ctrl_bijection.3121157547 |
|
|
May 28 03:26:58 AM PDT 23 |
May 28 03:27:13 AM PDT 23 |
288269561 ps |
| T17 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1808684719 |
|
|
May 28 03:28:20 AM PDT 23 |
May 28 03:33:09 AM PDT 23 |
12028618485 ps |
| T15 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2926729529 |
|
|
May 28 03:28:24 AM PDT 23 |
May 28 03:28:30 AM PDT 23 |
169235945 ps |
| T70 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2471818812 |
|
|
May 28 03:24:10 AM PDT 23 |
May 28 03:36:59 AM PDT 23 |
27146097984 ps |
| T30 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.627311474 |
|
|
May 28 03:25:51 AM PDT 23 |
May 28 03:25:52 AM PDT 23 |
69635672 ps |
| T28 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1557221164 |
|
|
May 28 03:27:04 AM PDT 23 |
May 28 04:24:44 AM PDT 23 |
1120445599 ps |
| T71 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.4071819307 |
|
|
May 28 03:23:07 AM PDT 23 |
May 28 03:23:10 AM PDT 23 |
192571514 ps |
| T20 |
/workspace/coverage/default/18.sram_ctrl_alert_test.1034297986 |
|
|
May 28 03:24:13 AM PDT 23 |
May 28 03:24:14 AM PDT 23 |
13978795 ps |
| T8 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4166372920 |
|
|
May 28 03:23:04 AM PDT 23 |
May 28 03:23:09 AM PDT 23 |
367408195 ps |
| T129 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2260038057 |
|
|
May 28 03:26:01 AM PDT 23 |
May 28 03:26:46 AM PDT 23 |
391591256 ps |
| T125 |
/workspace/coverage/default/26.sram_ctrl_smoke.1566826694 |
|
|
May 28 03:25:55 AM PDT 23 |
May 28 03:26:03 AM PDT 23 |
513842172 ps |
| T130 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3063212569 |
|
|
May 28 03:29:08 AM PDT 23 |
May 28 03:30:01 AM PDT 23 |
136868490 ps |
| T96 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.295843099 |
|
|
May 28 03:28:22 AM PDT 23 |
May 28 03:33:51 AM PDT 23 |
13642754988 ps |
| T7 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2667735661 |
|
|
May 28 03:25:00 AM PDT 23 |
May 28 03:25:05 AM PDT 23 |
687561836 ps |
| T27 |
/workspace/coverage/default/6.sram_ctrl_stress_all.1701542002 |
|
|
May 28 03:22:21 AM PDT 23 |
May 28 03:53:45 AM PDT 23 |
15906342454 ps |
| T64 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.2664407782 |
|
|
May 28 03:27:03 AM PDT 23 |
May 28 03:27:05 AM PDT 23 |
387834240 ps |
| T65 |
/workspace/coverage/default/31.sram_ctrl_smoke.2959099731 |
|
|
May 28 03:27:01 AM PDT 23 |
May 28 03:29:27 AM PDT 23 |
779510703 ps |
| T120 |
/workspace/coverage/default/41.sram_ctrl_executable.106503415 |
|
|
May 28 03:30:25 AM PDT 23 |
May 28 03:34:26 AM PDT 23 |
782199747 ps |
| T97 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1736272330 |
|
|
May 28 03:28:51 AM PDT 23 |
May 28 03:33:05 AM PDT 23 |
3610043545 ps |
| T131 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1167374299 |
|
|
May 28 03:26:04 AM PDT 23 |
May 28 03:27:17 AM PDT 23 |
8489193109 ps |
| T21 |
/workspace/coverage/default/42.sram_ctrl_alert_test.3431829526 |
|
|
May 28 03:30:22 AM PDT 23 |
May 28 03:30:23 AM PDT 23 |
35723629 ps |
| T132 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1125289818 |
|
|
May 28 03:23:23 AM PDT 23 |
May 28 03:24:22 AM PDT 23 |
127782933 ps |
| T133 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2077408067 |
|
|
May 28 03:23:05 AM PDT 23 |
May 28 03:24:42 AM PDT 23 |
276313558 ps |
| T31 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.2173075761 |
|
|
May 28 03:30:24 AM PDT 23 |
May 28 03:30:25 AM PDT 23 |
52436929 ps |
| T126 |
/workspace/coverage/default/43.sram_ctrl_smoke.2518507396 |
|
|
May 28 03:30:21 AM PDT 23 |
May 28 03:30:26 AM PDT 23 |
587419198 ps |
| T134 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.931255518 |
|
|
May 28 03:21:35 AM PDT 23 |
May 28 03:22:26 AM PDT 23 |
1142060012 ps |
| T123 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3861859456 |
|
|
May 28 03:22:34 AM PDT 23 |
May 28 03:51:51 AM PDT 23 |
36828805542 ps |
| T29 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3673396956 |
|
|
May 28 03:26:28 AM PDT 23 |
May 28 03:43:19 AM PDT 23 |
4977908758 ps |
| T25 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2237526146 |
|
|
May 28 03:24:08 AM PDT 23 |
May 28 04:09:17 AM PDT 23 |
14408335891 ps |
| T105 |
/workspace/coverage/default/45.sram_ctrl_bijection.1822973739 |
|
|
May 28 03:31:56 AM PDT 23 |
May 28 03:32:32 AM PDT 23 |
6654689054 ps |
| T106 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.842865410 |
|
|
May 28 03:27:09 AM PDT 23 |
May 28 03:27:10 AM PDT 23 |
30130106 ps |
| T107 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3889309614 |
|
|
May 28 03:28:17 AM PDT 23 |
May 28 03:38:31 AM PDT 23 |
4391249193 ps |
| T108 |
/workspace/coverage/default/49.sram_ctrl_stress_all.3558815840 |
|
|
May 28 03:33:50 AM PDT 23 |
May 28 04:40:21 AM PDT 23 |
39936964236 ps |
| T109 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.1466454909 |
|
|
May 28 03:24:58 AM PDT 23 |
May 28 03:25:35 AM PDT 23 |
440673225 ps |
| T110 |
/workspace/coverage/default/18.sram_ctrl_smoke.317259103 |
|
|
May 28 03:24:08 AM PDT 23 |
May 28 03:25:33 AM PDT 23 |
2339900554 ps |
| T135 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2172716454 |
|
|
May 28 03:30:21 AM PDT 23 |
May 28 03:30:22 AM PDT 23 |
88485418 ps |
| T98 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1063902004 |
|
|
May 28 03:25:11 AM PDT 23 |
May 28 03:28:37 AM PDT 23 |
2141660020 ps |
| T136 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3045052540 |
|
|
May 28 03:31:59 AM PDT 23 |
May 28 03:32:19 AM PDT 23 |
1971044049 ps |
| T137 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.2102420658 |
|
|
May 28 03:27:04 AM PDT 23 |
May 28 03:27:15 AM PDT 23 |
505375714 ps |
| T138 |
/workspace/coverage/default/17.sram_ctrl_regwen.2347463572 |
|
|
May 28 03:24:09 AM PDT 23 |
May 28 03:37:35 AM PDT 23 |
33269603071 ps |
| T139 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3528134900 |
|
|
May 28 03:28:45 AM PDT 23 |
May 28 03:28:46 AM PDT 23 |
59233779 ps |
| T140 |
/workspace/coverage/default/16.sram_ctrl_alert_test.973957576 |
|
|
May 28 03:23:09 AM PDT 23 |
May 28 03:23:10 AM PDT 23 |
23650506 ps |
| T75 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.19730294 |
|
|
May 28 03:30:31 AM PDT 23 |
May 28 03:30:36 AM PDT 23 |
582036740 ps |
| T47 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2259456822 |
|
|
May 28 03:22:13 AM PDT 23 |
May 28 04:55:08 AM PDT 23 |
11818965464 ps |
| T99 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3879275942 |
|
|
May 28 03:30:32 AM PDT 23 |
May 28 03:34:50 AM PDT 23 |
3052568184 ps |
| T141 |
/workspace/coverage/default/6.sram_ctrl_executable.3528068234 |
|
|
May 28 03:22:24 AM PDT 23 |
May 28 03:36:06 AM PDT 23 |
3429260249 ps |
| T142 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.4291137891 |
|
|
May 28 03:26:04 AM PDT 23 |
May 28 03:28:06 AM PDT 23 |
194703886 ps |
| T76 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2364751683 |
|
|
May 28 03:21:36 AM PDT 23 |
May 28 03:21:41 AM PDT 23 |
68753508 ps |
| T43 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1383759516 |
|
|
May 28 03:22:59 AM PDT 23 |
May 28 04:07:46 AM PDT 23 |
1748176742 ps |
| T143 |
/workspace/coverage/default/44.sram_ctrl_smoke.3140504291 |
|
|
May 28 03:31:53 AM PDT 23 |
May 28 03:32:25 AM PDT 23 |
85617798 ps |
| T18 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.418395344 |
|
|
May 28 03:30:22 AM PDT 23 |
May 28 03:44:24 AM PDT 23 |
26584270435 ps |
| T144 |
/workspace/coverage/default/49.sram_ctrl_smoke.3619504032 |
|
|
May 28 03:32:34 AM PDT 23 |
May 28 03:34:07 AM PDT 23 |
544122800 ps |
| T145 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.106335773 |
|
|
May 28 03:31:59 AM PDT 23 |
May 28 03:32:42 AM PDT 23 |
99890582 ps |
| T26 |
/workspace/coverage/default/37.sram_ctrl_regwen.1806922300 |
|
|
May 28 03:28:52 AM PDT 23 |
May 28 03:55:08 AM PDT 23 |
14275086971 ps |
| T19 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1801317939 |
|
|
May 28 03:26:05 AM PDT 23 |
May 28 03:34:33 AM PDT 23 |
4806543464 ps |
| T146 |
/workspace/coverage/default/27.sram_ctrl_stress_all.71737847 |
|
|
May 28 03:26:11 AM PDT 23 |
May 28 03:27:01 AM PDT 23 |
5446173548 ps |
| T111 |
/workspace/coverage/default/42.sram_ctrl_stress_all.2266654814 |
|
|
May 28 03:30:28 AM PDT 23 |
May 28 04:31:52 AM PDT 23 |
219085292072 ps |
| T48 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.353401974 |
|
|
May 28 03:23:08 AM PDT 23 |
May 28 03:41:27 AM PDT 23 |
653209818 ps |
| T147 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1713570448 |
|
|
May 28 03:24:16 AM PDT 23 |
May 28 03:24:17 AM PDT 23 |
46104348 ps |
| T148 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.738248348 |
|
|
May 28 03:28:48 AM PDT 23 |
May 28 03:28:53 AM PDT 23 |
1148144373 ps |
| T149 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.296826080 |
|
|
May 28 03:23:02 AM PDT 23 |
May 28 03:48:35 AM PDT 23 |
64673607086 ps |
| T150 |
/workspace/coverage/default/8.sram_ctrl_regwen.1595671509 |
|
|
May 28 03:22:25 AM PDT 23 |
May 28 03:25:13 AM PDT 23 |
486179651 ps |
| T151 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1281382445 |
|
|
May 28 03:22:20 AM PDT 23 |
May 28 03:22:21 AM PDT 23 |
44949697 ps |
| T152 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2777789685 |
|
|
May 28 03:21:31 AM PDT 23 |
May 28 03:21:32 AM PDT 23 |
83221257 ps |
| T153 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.270358608 |
|
|
May 28 03:28:47 AM PDT 23 |
May 28 03:29:30 AM PDT 23 |
216824575 ps |
| T49 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1259014575 |
|
|
May 28 03:25:56 AM PDT 23 |
May 28 03:47:43 AM PDT 23 |
2193847656 ps |
| T154 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.3710366854 |
|
|
May 28 03:22:21 AM PDT 23 |
May 28 03:22:22 AM PDT 23 |
27693063 ps |
| T100 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1398410619 |
|
|
May 28 03:28:25 AM PDT 23 |
May 28 03:35:50 AM PDT 23 |
24480100721 ps |
| T155 |
/workspace/coverage/default/4.sram_ctrl_bijection.1276237681 |
|
|
May 28 03:21:25 AM PDT 23 |
May 28 03:22:16 AM PDT 23 |
1642652910 ps |
| T156 |
/workspace/coverage/default/31.sram_ctrl_executable.3152468965 |
|
|
May 28 03:27:03 AM PDT 23 |
May 28 03:33:40 AM PDT 23 |
5312968842 ps |
| T157 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.1275106180 |
|
|
May 28 03:24:07 AM PDT 23 |
May 28 03:24:13 AM PDT 23 |
919253613 ps |
| T127 |
/workspace/coverage/default/16.sram_ctrl_partial_access.420474960 |
|
|
May 28 03:23:03 AM PDT 23 |
May 28 03:23:56 AM PDT 23 |
1740090766 ps |
| T158 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3618183820 |
|
|
May 28 03:21:23 AM PDT 23 |
May 28 03:21:24 AM PDT 23 |
34126649 ps |
| T159 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1302670690 |
|
|
May 28 03:25:03 AM PDT 23 |
May 28 03:25:49 AM PDT 23 |
220451827 ps |
| T160 |
/workspace/coverage/default/28.sram_ctrl_bijection.4152212159 |
|
|
May 28 03:26:19 AM PDT 23 |
May 28 03:26:43 AM PDT 23 |
2312815264 ps |
| T161 |
/workspace/coverage/default/1.sram_ctrl_smoke.2409007868 |
|
|
May 28 03:21:34 AM PDT 23 |
May 28 03:21:45 AM PDT 23 |
159479256 ps |
| T77 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3725653237 |
|
|
May 28 03:22:12 AM PDT 23 |
May 28 03:22:18 AM PDT 23 |
334031178 ps |
| T101 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2681672199 |
|
|
May 28 03:31:53 AM PDT 23 |
May 28 03:35:40 AM PDT 23 |
2370345495 ps |
| T162 |
/workspace/coverage/default/37.sram_ctrl_smoke.3435707976 |
|
|
May 28 03:28:51 AM PDT 23 |
May 28 03:29:14 AM PDT 23 |
1179942966 ps |
| T163 |
/workspace/coverage/default/28.sram_ctrl_alert_test.1059878897 |
|
|
May 28 03:26:24 AM PDT 23 |
May 28 03:26:26 AM PDT 23 |
20931376 ps |
| T124 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2973237347 |
|
|
May 28 03:27:10 AM PDT 23 |
May 28 03:32:35 AM PDT 23 |
14664200612 ps |
| T164 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2074321191 |
|
|
May 28 03:31:57 AM PDT 23 |
May 28 03:38:32 AM PDT 23 |
8212203619 ps |
| T121 |
/workspace/coverage/default/22.sram_ctrl_regwen.2217459287 |
|
|
May 28 03:25:15 AM PDT 23 |
May 28 03:57:15 AM PDT 23 |
21853129601 ps |
| T78 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3977238416 |
|
|
May 28 03:25:54 AM PDT 23 |
May 28 03:40:54 AM PDT 23 |
4085410785 ps |
| T165 |
/workspace/coverage/default/12.sram_ctrl_stress_all.733503902 |
|
|
May 28 03:23:06 AM PDT 23 |
May 28 04:30:48 AM PDT 23 |
35290374138 ps |
| T166 |
/workspace/coverage/default/3.sram_ctrl_regwen.3730185878 |
|
|
May 28 03:21:28 AM PDT 23 |
May 28 03:38:41 AM PDT 23 |
42258482164 ps |
| T128 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3752822432 |
|
|
May 28 03:24:10 AM PDT 23 |
May 28 03:49:20 AM PDT 23 |
177894169640 ps |
| T167 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.3313074669 |
|
|
May 28 03:22:25 AM PDT 23 |
May 28 03:22:28 AM PDT 23 |
202944628 ps |
| T168 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.237347529 |
|
|
May 28 03:28:23 AM PDT 23 |
May 28 03:28:28 AM PDT 23 |
472636250 ps |
| T169 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.4102467 |
|
|
May 28 03:26:08 AM PDT 23 |
May 28 03:29:57 AM PDT 23 |
20868311886 ps |
| T170 |
/workspace/coverage/default/41.sram_ctrl_regwen.2482286241 |
|
|
May 28 03:30:30 AM PDT 23 |
May 28 03:41:01 AM PDT 23 |
3937170636 ps |
| T50 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2670163394 |
|
|
May 28 02:09:13 AM PDT 23 |
May 28 02:09:17 AM PDT 23 |
81639846 ps |
| T54 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2331191691 |
|
|
May 28 02:09:03 AM PDT 23 |
May 28 02:09:06 AM PDT 23 |
205803552 ps |
| T44 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1651110376 |
|
|
May 28 02:09:08 AM PDT 23 |
May 28 02:09:11 AM PDT 23 |
324327834 ps |
| T102 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.4020540336 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:04 AM PDT 23 |
36748557 ps |
| T103 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.616120956 |
|
|
May 28 02:09:05 AM PDT 23 |
May 28 02:09:06 AM PDT 23 |
29388548 ps |
| T51 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3225896320 |
|
|
May 28 02:09:12 AM PDT 23 |
May 28 02:09:13 AM PDT 23 |
35509725 ps |
| T45 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3949904850 |
|
|
May 28 02:10:18 AM PDT 23 |
May 28 02:10:21 AM PDT 23 |
671524483 ps |
| T93 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3430846656 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
24288706 ps |
| T46 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2575991886 |
|
|
May 28 02:09:03 AM PDT 23 |
May 28 02:09:06 AM PDT 23 |
224769188 ps |
| T55 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3500558820 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:26 AM PDT 23 |
37801447 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3516041765 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:31 AM PDT 23 |
452204081 ps |
| T171 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1369480569 |
|
|
May 28 02:08:58 AM PDT 23 |
May 28 02:09:00 AM PDT 23 |
125100572 ps |
| T52 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3097324376 |
|
|
May 28 02:10:27 AM PDT 23 |
May 28 02:10:30 AM PDT 23 |
113968140 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.732663449 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:05 AM PDT 23 |
45244281 ps |
| T56 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3301580822 |
|
|
May 28 02:10:19 AM PDT 23 |
May 28 02:10:20 AM PDT 23 |
15215840 ps |
| T172 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3275580081 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:28 AM PDT 23 |
136475952 ps |
| T104 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.887869265 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
15909103 ps |
| T57 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1838199646 |
|
|
May 28 02:10:39 AM PDT 23 |
May 28 02:10:45 AM PDT 23 |
825936074 ps |
| T58 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.510176596 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
24143371 ps |
| T59 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.41479383 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
40748307 ps |
| T60 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1292683960 |
|
|
May 28 02:10:39 AM PDT 23 |
May 28 02:10:40 AM PDT 23 |
50819615 ps |
| T61 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.864065757 |
|
|
May 28 02:10:35 AM PDT 23 |
May 28 02:10:36 AM PDT 23 |
33000492 ps |
| T62 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2127281005 |
|
|
May 28 02:10:19 AM PDT 23 |
May 28 02:10:21 AM PDT 23 |
155719637 ps |
| T63 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1467589674 |
|
|
May 28 02:10:17 AM PDT 23 |
May 28 02:10:21 AM PDT 23 |
292657916 ps |
| T66 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.122711152 |
|
|
May 28 02:10:23 AM PDT 23 |
May 28 02:10:30 AM PDT 23 |
1090748819 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.233559125 |
|
|
May 28 02:10:37 AM PDT 23 |
May 28 02:10:38 AM PDT 23 |
13463082 ps |
| T68 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3525394529 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:05 AM PDT 23 |
67229190 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1465293291 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:05 AM PDT 23 |
58489653 ps |
| T72 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.996904741 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:31 AM PDT 23 |
424217566 ps |
| T73 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3960906635 |
|
|
May 28 02:10:39 AM PDT 23 |
May 28 02:10:41 AM PDT 23 |
79455621 ps |
| T74 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.466222767 |
|
|
May 28 02:09:01 AM PDT 23 |
May 28 02:09:02 AM PDT 23 |
54013301 ps |
| T87 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.4184303555 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
45777282 ps |
| T90 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2358747969 |
|
|
May 28 02:10:23 AM PDT 23 |
May 28 02:10:28 AM PDT 23 |
159892137 ps |
| T173 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.34596637 |
|
|
May 28 02:10:36 AM PDT 23 |
May 28 02:10:37 AM PDT 23 |
38517261 ps |
| T79 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3044488618 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:05 AM PDT 23 |
25825268 ps |
| T174 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2755555679 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
27396431 ps |
| T175 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2079297430 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:30 AM PDT 23 |
1742014875 ps |
| T176 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1889135640 |
|
|
May 28 02:10:27 AM PDT 23 |
May 28 02:10:29 AM PDT 23 |
15427644 ps |
| T177 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3517290677 |
|
|
May 28 02:10:29 AM PDT 23 |
May 28 02:10:31 AM PDT 23 |
95147235 ps |
| T80 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.4077057611 |
|
|
May 28 02:10:36 AM PDT 23 |
May 28 02:10:43 AM PDT 23 |
551858813 ps |
| T178 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2731856964 |
|
|
May 28 02:10:21 AM PDT 23 |
May 28 02:10:23 AM PDT 23 |
24444406 ps |
| T179 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3576559533 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
82156323 ps |
| T180 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.588117322 |
|
|
May 28 02:10:29 AM PDT 23 |
May 28 02:10:31 AM PDT 23 |
134987350 ps |
| T181 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3002807590 |
|
|
May 28 02:09:09 AM PDT 23 |
May 28 02:09:11 AM PDT 23 |
127649636 ps |
| T182 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2881073667 |
|
|
May 28 02:09:12 AM PDT 23 |
May 28 02:09:12 AM PDT 23 |
115482809 ps |
| T183 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.552032004 |
|
|
May 28 02:09:01 AM PDT 23 |
May 28 02:09:06 AM PDT 23 |
132905821 ps |
| T81 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3319591246 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:31 AM PDT 23 |
474033485 ps |
| T184 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.853020333 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:05 AM PDT 23 |
27378008 ps |
| T185 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.761645298 |
|
|
May 28 02:10:17 AM PDT 23 |
May 28 02:10:18 AM PDT 23 |
21944724 ps |
| T115 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2298092110 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:28 AM PDT 23 |
130583233 ps |
| T186 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3285982075 |
|
|
May 28 02:10:22 AM PDT 23 |
May 28 02:10:23 AM PDT 23 |
72650380 ps |
| T187 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3693800355 |
|
|
May 28 02:08:59 AM PDT 23 |
May 28 02:09:04 AM PDT 23 |
164217929 ps |
| T188 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3959680165 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:26 AM PDT 23 |
44223942 ps |
| T114 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.478063707 |
|
|
May 28 02:09:02 AM PDT 23 |
May 28 02:09:04 AM PDT 23 |
140242467 ps |
| T189 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2027630896 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:06 AM PDT 23 |
145697991 ps |
| T190 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1667118077 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:07 AM PDT 23 |
50648182 ps |
| T191 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1492360827 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
48129823 ps |
| T192 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1053016516 |
|
|
May 28 02:10:36 AM PDT 23 |
May 28 02:10:41 AM PDT 23 |
141958549 ps |
| T117 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.808011690 |
|
|
May 28 02:09:01 AM PDT 23 |
May 28 02:09:03 AM PDT 23 |
153210145 ps |
| T119 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2237819514 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
306658131 ps |
| T82 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3953549014 |
|
|
May 28 02:10:35 AM PDT 23 |
May 28 02:10:36 AM PDT 23 |
20240482 ps |
| T193 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2573097390 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
15670896 ps |
| T194 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.843632044 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
193878000 ps |
| T195 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2287403743 |
|
|
May 28 02:10:29 AM PDT 23 |
May 28 02:10:31 AM PDT 23 |
59336413 ps |
| T196 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2140155614 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
39131322 ps |
| T197 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2407191177 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:26 AM PDT 23 |
168510674 ps |
| T85 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2572337166 |
|
|
May 28 02:10:35 AM PDT 23 |
May 28 02:10:46 AM PDT 23 |
2324559533 ps |
| T198 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3890015884 |
|
|
May 28 02:08:46 AM PDT 23 |
May 28 02:08:48 AM PDT 23 |
576639746 ps |
| T199 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1133234432 |
|
|
May 28 02:10:22 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
181181211 ps |
| T200 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.26445936 |
|
|
May 28 02:10:37 AM PDT 23 |
May 28 02:10:43 AM PDT 23 |
755402843 ps |
| T201 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1563071636 |
|
|
May 28 02:08:58 AM PDT 23 |
May 28 02:09:02 AM PDT 23 |
46741181 ps |
| T202 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1841529655 |
|
|
May 28 02:10:23 AM PDT 23 |
May 28 02:10:24 AM PDT 23 |
20140033 ps |
| T116 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2292571689 |
|
|
May 28 02:10:22 AM PDT 23 |
May 28 02:10:24 AM PDT 23 |
133058620 ps |
| T203 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.724150745 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:08 AM PDT 23 |
221956379 ps |
| T113 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3372934501 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:26 AM PDT 23 |
518501994 ps |
| T204 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3273864743 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:07 AM PDT 23 |
139296946 ps |
| T205 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.199209876 |
|
|
May 28 02:10:30 AM PDT 23 |
May 28 02:10:34 AM PDT 23 |
108444702 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.752889488 |
|
|
May 28 02:09:09 AM PDT 23 |
May 28 02:09:20 AM PDT 23 |
1524265814 ps |
| T88 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4260833301 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:29 AM PDT 23 |
400766019 ps |
| T206 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3885975334 |
|
|
May 28 02:09:03 AM PDT 23 |
May 28 02:09:06 AM PDT 23 |
244685770 ps |
| T207 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.768202568 |
|
|
May 28 02:09:09 AM PDT 23 |
May 28 02:09:11 AM PDT 23 |
49316716 ps |
| T208 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4104958172 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:29 AM PDT 23 |
464084985 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.97396111 |
|
|
May 28 02:10:35 AM PDT 23 |
May 28 02:10:42 AM PDT 23 |
602681224 ps |
| T209 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4157332619 |
|
|
May 28 02:09:03 AM PDT 23 |
May 28 02:09:04 AM PDT 23 |
14839430 ps |
| T210 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2277718349 |
|
|
May 28 02:10:39 AM PDT 23 |
May 28 02:10:40 AM PDT 23 |
16778671 ps |
| T211 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.188965902 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:30 AM PDT 23 |
373949070 ps |
| T212 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4071363059 |
|
|
May 28 02:09:08 AM PDT 23 |
May 28 02:09:09 AM PDT 23 |
22082493 ps |
| T213 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4179514547 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:28 AM PDT 23 |
71614447 ps |
| T214 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3054074592 |
|
|
May 28 02:09:02 AM PDT 23 |
May 28 02:09:04 AM PDT 23 |
118747666 ps |
| T215 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4065053294 |
|
|
May 28 02:10:36 AM PDT 23 |
May 28 02:10:41 AM PDT 23 |
603424171 ps |
| T216 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4267402157 |
|
|
May 28 02:09:05 AM PDT 23 |
May 28 02:09:06 AM PDT 23 |
45659765 ps |
| T217 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.344296186 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
38449257 ps |
| T218 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3489665022 |
|
|
May 28 02:10:22 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
844397862 ps |
| T219 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3806529561 |
|
|
May 28 02:10:36 AM PDT 23 |
May 28 02:10:37 AM PDT 23 |
42160341 ps |
| T220 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1445769686 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
86727062 ps |
| T221 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2053349671 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:26 AM PDT 23 |
17523123 ps |
| T222 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3155983905 |
|
|
May 28 02:09:01 AM PDT 23 |
May 28 02:09:03 AM PDT 23 |
23009057 ps |
| T223 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2339666879 |
|
|
May 28 02:09:01 AM PDT 23 |
May 28 02:09:02 AM PDT 23 |
25818106 ps |
| T224 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2814649755 |
|
|
May 28 02:09:08 AM PDT 23 |
May 28 02:09:09 AM PDT 23 |
27533847 ps |
| T225 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.774242569 |
|
|
May 28 02:09:08 AM PDT 23 |
May 28 02:09:10 AM PDT 23 |
41572522 ps |
| T226 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3111124887 |
|
|
May 28 02:10:39 AM PDT 23 |
May 28 02:10:40 AM PDT 23 |
18651708 ps |
| T227 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3320797300 |
|
|
May 28 02:10:23 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
48346230 ps |
| T228 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3945453821 |
|
|
May 28 02:10:39 AM PDT 23 |
May 28 02:10:40 AM PDT 23 |
61387057 ps |
| T229 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1279720055 |
|
|
May 28 02:10:22 AM PDT 23 |
May 28 02:10:26 AM PDT 23 |
134963509 ps |
| T91 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1126453380 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:28 AM PDT 23 |
23713574 ps |
| T230 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2821876493 |
|
|
May 28 02:10:23 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
458467764 ps |
| T231 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4232557417 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:26 AM PDT 23 |
196180492 ps |
| T232 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2905041442 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
57388151 ps |
| T233 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3588583226 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:29 AM PDT 23 |
41371339 ps |
| T92 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2569357099 |
|
|
May 28 02:09:01 AM PDT 23 |
May 28 02:09:13 AM PDT 23 |
1508059419 ps |
| T234 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2750580753 |
|
|
May 28 02:09:01 AM PDT 23 |
May 28 02:09:04 AM PDT 23 |
240078324 ps |
| T235 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1409933694 |
|
|
May 28 02:09:05 AM PDT 23 |
May 28 02:09:06 AM PDT 23 |
14792517 ps |
| T236 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2511185655 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:29 AM PDT 23 |
261985647 ps |
| T237 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2267432877 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:05 AM PDT 23 |
24949705 ps |
| T238 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2132916745 |
|
|
May 28 02:10:22 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
612078559 ps |
| T239 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3209222737 |
|
|
May 28 02:09:08 AM PDT 23 |
May 28 02:09:09 AM PDT 23 |
41063928 ps |
| T240 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3523840998 |
|
|
May 28 02:10:03 AM PDT 23 |
May 28 02:10:13 AM PDT 23 |
831276939 ps |
| T241 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.849931803 |
|
|
May 28 02:10:25 AM PDT 23 |
May 28 02:10:27 AM PDT 23 |
34908658 ps |
| T242 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3563671810 |
|
|
May 28 02:10:36 AM PDT 23 |
May 28 02:10:39 AM PDT 23 |
738714525 ps |
| T243 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3965045500 |
|
|
May 28 02:09:05 AM PDT 23 |
May 28 02:09:07 AM PDT 23 |
14579916 ps |
| T244 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.682994005 |
|
|
May 28 02:10:23 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
85439187 ps |
| T245 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3098249552 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:05 AM PDT 23 |
177156007 ps |
| T118 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2188048620 |
|
|
May 28 02:10:26 AM PDT 23 |
May 28 02:10:28 AM PDT 23 |
99480609 ps |
| T246 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1345402687 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
45128784 ps |
| T247 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3419107741 |
|
|
May 28 02:09:05 AM PDT 23 |
May 28 02:09:08 AM PDT 23 |
68490139 ps |
| T248 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3272901440 |
|
|
May 28 02:10:24 AM PDT 23 |
May 28 02:10:25 AM PDT 23 |
418276840 ps |
| T249 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2905360863 |
|
|
May 28 02:10:33 AM PDT 23 |
May 28 02:10:36 AM PDT 23 |
28436556 ps |
| T250 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2599035749 |
|
|
May 28 02:10:18 AM PDT 23 |
May 28 02:10:21 AM PDT 23 |
897833757 ps |
| T251 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.418366038 |
|
|
May 28 02:09:04 AM PDT 23 |
May 28 02:09:07 AM PDT 23 |
440207952 ps |
| T252 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1842320778 |
|
|
May 28 02:10:18 AM PDT 23 |
May 28 02:10:19 AM PDT 23 |
38840711 ps |
| T253 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.167026190 |
|
|
May 28 02:10:38 AM PDT 23 |
May 28 02:10:39 AM PDT 23 |
37936041 ps |
| T254 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2721681494 |
|
|
May 28 02:10:36 AM PDT 23 |
May 28 02:10:39 AM PDT 23 |
115815887 ps |
| T255 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.25131538 |
|
|
May 28 02:09:05 AM PDT 23 |
May 28 02:09:07 AM PDT 23 |
26025094 ps |
| T256 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1492396107 |
|
|
May 28 02:10:36 AM PDT 23 |
May 28 02:10:37 AM PDT 23 |
15004412 ps |
| T257 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.929869967 |
|
|
May 28 02:10:23 AM PDT 23 |
May 28 02:10:24 AM PDT 23 |
143353513 ps |
| T258 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.883377248 |
|
|
May 28 03:23:04 AM PDT 23 |
May 28 03:28:09 AM PDT 23 |
3180538399 ps |
| T259 |
/workspace/coverage/default/5.sram_ctrl_regwen.3626618462 |
|
|
May 28 03:22:31 AM PDT 23 |
May 28 03:25:49 AM PDT 23 |
3086556023 ps |
| T260 |
/workspace/coverage/default/29.sram_ctrl_smoke.443432634 |
|
|
May 28 03:26:28 AM PDT 23 |
May 28 03:26:35 AM PDT 23 |
114189163 ps |
| T261 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1085671838 |
|
|
May 28 03:30:21 AM PDT 23 |
May 28 03:44:26 AM PDT 23 |
7485150264 ps |
| T262 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.4228330754 |
|
|
May 28 03:28:48 AM PDT 23 |
May 28 03:36:52 AM PDT 23 |
4679226964 ps |
| T263 |
/workspace/coverage/default/42.sram_ctrl_bijection.441747181 |
|
|
May 28 03:30:26 AM PDT 23 |
May 28 03:30:59 AM PDT 23 |
2441600564 ps |
| T83 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1017100024 |
|
|
May 28 03:30:17 AM PDT 23 |
May 28 03:30:22 AM PDT 23 |
559580513 ps |
| T84 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4085278182 |
|
|
May 28 03:26:26 AM PDT 23 |
May 28 03:26:32 AM PDT 23 |
171017336 ps |
| T264 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2650869952 |
|
|
May 28 03:30:20 AM PDT 23 |
May 28 03:37:30 AM PDT 23 |
169706860928 ps |
| T265 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.4011303508 |
|
|
May 28 03:23:05 AM PDT 23 |
May 28 03:23:07 AM PDT 23 |
86238704 ps |
| T266 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.958169641 |
|
|
May 28 03:23:04 AM PDT 23 |
May 28 03:23:07 AM PDT 23 |
44350359 ps |