Testbench Group List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
533 533 100.00 533 533 100.00 1


Total groups in report: 21
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 12 15 80.00 100.00 1 100 1 1 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 14 14 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg 24 24 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg 2 2 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'sb00000000000000000000000000000101,32'sb00000000000000000000000000001010)::mubi_cg 6 6 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg 6 6 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg 10 10 100.00 100.00 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg 42 42 100.00 100.00 1 100 1 1 64 64
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_if_proxy::onehot_fault_cg 3 3 100.00 100.00 1 100 1 1 64 64
push_pull_agent_pkg::req_ack_cg 3 3 100.00 100.00 1 100 1 1 64 64
sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::access_during_key_req_cg 2 2 100.00 1 100 1 0 64 64
sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg 25 25 100.00 1 100 1 0 64 64
sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::key_seed_valid_cg 8 8 100.00 1 100 1 0 64 64
sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::lc_escalation_idle_cg 2 2 100.00 1 100 1 0 64 64
sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg 17 17 100.00 1 100 1 0 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=2} 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%