| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.132382375 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.185528443 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2863377500 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1179768935 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2739209462 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3438562308 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3354283956 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2321855942 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4161860837 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1042316066 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1418934764 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3204634479 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3401073195 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.252302128 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1630189214 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1874666624 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3236713823 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3470140447 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.660606925 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.897819663 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3680506474 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3485670542 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4208093940 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2747401477 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.683025004 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2327206768 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3551917768 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.492745637 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2286330021 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2181286179 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.65868020 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.279423195 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2384322159 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3939268418 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4287647889 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2937227469 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2146550082 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2929534013 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.392553808 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4176851077 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1135376685 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.284160920 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3970550929 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.797743512 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.97604831 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1283551326 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.998753126 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2368461407 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.836326408 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2235538557 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.270353769 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1576415515 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.389111549 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2941403686 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4025823346 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1872789374 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4190330140 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3309955606 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1278616760 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2059470530 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2506645147 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1970643980 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.370741994 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3063007821 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1324108161 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2795682835 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3041040307 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.791932996 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3372474384 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3444886953 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2936644489 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2005060517 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3548239408 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2406643535 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2372490307 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1993591871 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1296754160 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1123247551 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1707882617 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1890677415 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.380823849 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2108065934 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1906100471 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.657980462 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3751228254 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.16671422 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.636708757 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3320515584 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2848813053 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1973012966 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2216129231 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3257711210 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2226274975 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2800645218 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2864448057 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2749231277 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1155223895 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.23337443 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2585964284 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.856433306 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2971595805 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.970743103 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1315128934 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3364088710 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2628427220 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1176447434 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3763574747 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1826117909 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.998848574 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2328900036 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3839309990 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.539300999 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1434641452 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1442816793 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2273248839 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2222951499 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1393424502 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2058582080 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.925427905 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3962168722 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.831777658 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1369274597 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1593810309 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.231937681 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2340190426 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2675931932 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1375972469 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1288676476 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2724575430 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3770539374 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.2522090660 |
| /workspace/coverage/default/0.sram_ctrl_bijection.3601195155 |
| /workspace/coverage/default/0.sram_ctrl_executable.2651692091 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.3058874591 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1978838959 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1736821047 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.3449237603 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3931302319 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3987469743 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3266342243 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1081432024 |
| /workspace/coverage/default/0.sram_ctrl_regwen.2253528790 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.1382550290 |
| /workspace/coverage/default/0.sram_ctrl_smoke.2873572700 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.2930702213 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2864648974 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.614106692 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2947353431 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.1675299195 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.502383318 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3598972613 |
| /workspace/coverage/default/1.sram_ctrl_executable.3650566132 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.1523579684 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.4093967104 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.3572528595 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.2772065904 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.3256940193 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.1577338209 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3938710171 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.715461250 |
| /workspace/coverage/default/1.sram_ctrl_regwen.3895499041 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.3944954055 |
| /workspace/coverage/default/1.sram_ctrl_smoke.1602373777 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.1490331738 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.353500366 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.921499376 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4141089581 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3693281275 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.3307705676 |
| /workspace/coverage/default/10.sram_ctrl_bijection.832662482 |
| /workspace/coverage/default/10.sram_ctrl_executable.301101535 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.3931773535 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3150025869 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1966089240 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.147116236 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.2109854907 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.1544298262 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3778723203 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.3215347961 |
| /workspace/coverage/default/10.sram_ctrl_regwen.2166419066 |
| /workspace/coverage/default/10.sram_ctrl_smoke.2798497748 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.4090718304 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2700330088 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1451115959 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3628412749 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1803507173 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.1232094533 |
| /workspace/coverage/default/11.sram_ctrl_bijection.230763567 |
| /workspace/coverage/default/11.sram_ctrl_executable.17445890 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.543882647 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1460256383 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.508039161 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.3547111783 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.2149429312 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.847143312 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.766996948 |
| /workspace/coverage/default/11.sram_ctrl_regwen.981895505 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1357493834 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.3523416311 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.28857848 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.445731487 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1100910002 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3729226702 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.3960582347 |
| /workspace/coverage/default/12.sram_ctrl_bijection.994120803 |
| /workspace/coverage/default/12.sram_ctrl_executable.2518170805 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.1430098436 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.1596146574 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2033981350 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.4196931178 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.359654556 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.4072313526 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2006997008 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.3511923240 |
| /workspace/coverage/default/12.sram_ctrl_regwen.4052871913 |
| /workspace/coverage/default/12.sram_ctrl_smoke.3912510278 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.447399466 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.843413966 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.163501987 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.122024524 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.1743608182 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.3556030202 |
| /workspace/coverage/default/13.sram_ctrl_bijection.1603089671 |
| /workspace/coverage/default/13.sram_ctrl_executable.1175336887 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.1620174386 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1255191605 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.784129636 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.1535651579 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.698167944 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.2348043373 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.458826244 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1824679556 |
| /workspace/coverage/default/13.sram_ctrl_regwen.3358134855 |
| /workspace/coverage/default/13.sram_ctrl_smoke.3043129732 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2409051583 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3074492631 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.876929575 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2388339319 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.476967327 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2931353564 |
| /workspace/coverage/default/14.sram_ctrl_executable.1501183760 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.2871125352 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2654618770 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1669932401 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.2521382408 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.2841729774 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.1838948698 |
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| /workspace/coverage/default/42.sram_ctrl_partial_access.1778947509 |
| /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1483627503 |
| /workspace/coverage/default/42.sram_ctrl_ram_cfg.1941563269 |
| /workspace/coverage/default/42.sram_ctrl_regwen.4158537936 |
| /workspace/coverage/default/42.sram_ctrl_smoke.2399821807 |
| /workspace/coverage/default/42.sram_ctrl_stress_all.3012408899 |
| /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4153166432 |
| /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3146713778 |
| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.28596249 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.1957326604 |
| /workspace/coverage/default/43.sram_ctrl_bijection.4074278773 |
| /workspace/coverage/default/43.sram_ctrl_executable.3989210935 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.2710195583 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.2966585315 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2736000643 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.131915775 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.2930973707 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.1585617985 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2883373803 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.4019264108 |
| /workspace/coverage/default/43.sram_ctrl_regwen.3133344978 |
| /workspace/coverage/default/43.sram_ctrl_smoke.1468651663 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.448795873 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.718427862 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.3235579744 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2830153527 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3174743121 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.689916421 |
| /workspace/coverage/default/44.sram_ctrl_bijection.2812817028 |
| /workspace/coverage/default/44.sram_ctrl_executable.474106242 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.2156446701 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.2524165277 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3668257658 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.3025378013 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.2556751857 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.3938084567 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2896551058 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.656398251 |
| /workspace/coverage/default/44.sram_ctrl_regwen.3124643319 |
| /workspace/coverage/default/44.sram_ctrl_smoke.594706460 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.3297572160 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1086264155 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.528574738 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3347852360 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3641792261 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.2081804606 |
| /workspace/coverage/default/45.sram_ctrl_bijection.335864795 |
| /workspace/coverage/default/45.sram_ctrl_executable.653446527 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.956118089 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.3317967112 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.63480040 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.494278956 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.2529761919 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.1218167162 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1321752675 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.2595981348 |
| /workspace/coverage/default/45.sram_ctrl_regwen.2385379792 |
| /workspace/coverage/default/45.sram_ctrl_smoke.264012024 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.1323508008 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1807969458 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2344955806 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2817690919 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.4069776030 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.4106480845 |
| /workspace/coverage/default/46.sram_ctrl_bijection.3885270508 |
| /workspace/coverage/default/46.sram_ctrl_executable.3306162151 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.677163467 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.705450165 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2458853981 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.924909977 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.1744605355 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.4197775149 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4151667841 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.2534808080 |
| /workspace/coverage/default/46.sram_ctrl_regwen.2293484848 |
| /workspace/coverage/default/46.sram_ctrl_smoke.1452662175 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.3147335590 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2686939373 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1637411999 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3889748968 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.593199585 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.1393115384 |
| /workspace/coverage/default/47.sram_ctrl_bijection.3006071910 |
| /workspace/coverage/default/47.sram_ctrl_executable.1015920111 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.1297488881 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.1165157407 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1864248728 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.3084119132 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.284135308 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.3957472020 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3198479252 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.638949458 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3038286143 |
| /workspace/coverage/default/47.sram_ctrl_smoke.209141949 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.2188234957 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4211909982 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3264474883 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3268610583 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3201209763 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.2879606919 |
| /workspace/coverage/default/48.sram_ctrl_bijection.2543930968 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.1834340014 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.3419212209 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1210435764 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.1950144851 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.2336064602 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.2719211715 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3751283195 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.2372032951 |
| /workspace/coverage/default/48.sram_ctrl_regwen.4247154470 |
| /workspace/coverage/default/48.sram_ctrl_smoke.90189827 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.1141491089 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.669123733 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1499161733 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.603889308 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1403573678 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.3503690743 |
| /workspace/coverage/default/49.sram_ctrl_bijection.3934823507 |
| /workspace/coverage/default/49.sram_ctrl_executable.1529314911 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.2772256945 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.4078464102 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1015441841 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.2333344023 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.3986530064 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.2558185725 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2628305842 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.4103085046 |
| /workspace/coverage/default/49.sram_ctrl_regwen.1085453705 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1224872874 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3666442951 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2948163543 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.343090588 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2397348331 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4035405778 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.1916557456 |
| /workspace/coverage/default/5.sram_ctrl_bijection.1705180383 |
| /workspace/coverage/default/5.sram_ctrl_executable.1199267302 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.1444784001 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.1779791828 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3251385782 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.1503106628 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2621511577 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.2841972656 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1137610269 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.819058663 |
| /workspace/coverage/default/5.sram_ctrl_regwen.1380392852 |
| /workspace/coverage/default/5.sram_ctrl_smoke.3404309385 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.2666157604 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1078996765 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1188743035 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4216415685 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.207860151 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.293636583 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1197745071 |
| /workspace/coverage/default/6.sram_ctrl_executable.1076913997 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.2582882038 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.2532569551 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1014403377 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.2659801222 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.917626607 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.962768294 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.425769596 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.3546934406 |
| /workspace/coverage/default/6.sram_ctrl_regwen.2376221390 |
| /workspace/coverage/default/6.sram_ctrl_smoke.1465718353 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.1938466554 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.976712746 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.84554845 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3423781683 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2698776044 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.1622246744 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1547094272 |
| /workspace/coverage/default/7.sram_ctrl_executable.746504494 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.2778010686 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.715198138 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1425289439 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.1799211477 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1493095996 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.3432637214 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3141634958 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.2494491430 |
| /workspace/coverage/default/7.sram_ctrl_regwen.2246502462 |
| /workspace/coverage/default/7.sram_ctrl_smoke.2492556620 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.345473580 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.875574348 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1892902147 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4219270615 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2551288699 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.864262225 |
| /workspace/coverage/default/8.sram_ctrl_bijection.719524842 |
| /workspace/coverage/default/8.sram_ctrl_executable.140537429 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.1521885750 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.1967783494 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2989357124 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.381278811 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.2003865968 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.2624620179 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1049049402 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3786696785 |
| /workspace/coverage/default/8.sram_ctrl_regwen.2900740639 |
| /workspace/coverage/default/8.sram_ctrl_smoke.1999163525 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.32943062 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1275823056 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4018057151 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.678093652 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1509045004 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.2792259130 |
| /workspace/coverage/default/9.sram_ctrl_bijection.3824481581 |
| /workspace/coverage/default/9.sram_ctrl_executable.2244667461 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.2462092150 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.53950647 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1275114551 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.344332090 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3235885247 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.661974117 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2140395420 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1691359092 |
| /workspace/coverage/default/9.sram_ctrl_regwen.3405304801 |
| /workspace/coverage/default/9.sram_ctrl_smoke.1458062038 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3230745815 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2567927210 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.866537115 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1589448955 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/8.sram_ctrl_alert_test.864262225 |
|
|
May 29 01:12:26 AM PDT 23 |
May 29 01:12:29 AM PDT 23 |
23673339 ps |
| T2 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3797861760 |
|
|
May 29 01:30:05 AM PDT 23 |
May 29 01:30:10 AM PDT 23 |
308418114 ps |
| T3 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.917626607 |
|
|
May 29 01:12:28 AM PDT 23 |
May 29 01:34:11 AM PDT 23 |
88158827012 ps |
| T4 |
/workspace/coverage/default/20.sram_ctrl_smoke.1245245772 |
|
|
May 29 01:22:35 AM PDT 23 |
May 29 01:24:06 AM PDT 23 |
1849301908 ps |
| T9 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2003865968 |
|
|
May 29 01:12:32 AM PDT 23 |
May 29 01:26:52 AM PDT 23 |
4069310812 ps |
| T5 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2772256945 |
|
|
May 29 01:33:24 AM PDT 23 |
May 29 01:33:36 AM PDT 23 |
917616718 ps |
| T6 |
/workspace/coverage/default/48.sram_ctrl_executable.312938302 |
|
|
May 29 01:33:21 AM PDT 23 |
May 29 01:52:59 AM PDT 23 |
8711843132 ps |
| T7 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2778010686 |
|
|
May 29 01:12:29 AM PDT 23 |
May 29 01:12:37 AM PDT 23 |
554956664 ps |
| T10 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2821821614 |
|
|
May 29 01:10:35 AM PDT 23 |
May 29 01:14:46 AM PDT 23 |
5308150135 ps |
| T11 |
/workspace/coverage/default/26.sram_ctrl_executable.1557257162 |
|
|
May 29 01:29:01 AM PDT 23 |
May 29 01:40:49 AM PDT 23 |
18001677500 ps |
| T14 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2403190467 |
|
|
May 29 01:32:33 AM PDT 23 |
May 29 01:44:32 AM PDT 23 |
2065772035 ps |
| T15 |
/workspace/coverage/default/21.sram_ctrl_executable.3879700466 |
|
|
May 29 01:27:10 AM PDT 23 |
May 29 01:42:03 AM PDT 23 |
58191302386 ps |
| T107 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.3386974646 |
|
|
May 29 01:29:58 AM PDT 23 |
May 29 01:30:31 AM PDT 23 |
1143480010 ps |
| T24 |
/workspace/coverage/default/24.sram_ctrl_regwen.2800145962 |
|
|
May 29 01:27:53 AM PDT 23 |
May 29 01:31:27 AM PDT 23 |
12558856071 ps |
| T31 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.1474588544 |
|
|
May 29 01:30:05 AM PDT 23 |
May 29 01:30:07 AM PDT 23 |
82067519 ps |
| T13 |
/workspace/coverage/default/11.sram_ctrl_smoke.1357493834 |
|
|
May 29 01:14:48 AM PDT 23 |
May 29 01:15:04 AM PDT 23 |
850969007 ps |
| T76 |
/workspace/coverage/default/24.sram_ctrl_executable.490115130 |
|
|
May 29 01:27:50 AM PDT 23 |
May 29 02:01:57 AM PDT 23 |
38587549820 ps |
| T77 |
/workspace/coverage/default/29.sram_ctrl_executable.300301406 |
|
|
May 29 01:29:25 AM PDT 23 |
May 29 01:37:55 AM PDT 23 |
2931737975 ps |
| T25 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3297572160 |
|
|
May 29 01:32:25 AM PDT 23 |
May 29 01:54:52 AM PDT 23 |
20317021579 ps |
| T98 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.384686396 |
|
|
May 29 01:10:35 AM PDT 23 |
May 29 01:16:34 AM PDT 23 |
14416192712 ps |
| T32 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2459857084 |
|
|
May 29 01:28:25 AM PDT 23 |
May 29 01:28:26 AM PDT 23 |
27872107 ps |
| T99 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3751283195 |
|
|
May 29 01:32:51 AM PDT 23 |
May 29 01:39:31 AM PDT 23 |
23375210031 ps |
| T123 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.868007153 |
|
|
May 29 01:28:59 AM PDT 23 |
May 29 01:31:15 AM PDT 23 |
2112831537 ps |
| T16 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2649901688 |
|
|
May 29 01:25:28 AM PDT 23 |
May 29 01:30:32 AM PDT 23 |
8279451259 ps |
| T12 |
/workspace/coverage/default/27.sram_ctrl_executable.2957941849 |
|
|
May 29 01:28:47 AM PDT 23 |
May 29 01:55:03 AM PDT 23 |
132538860354 ps |
| T26 |
/workspace/coverage/default/36.sram_ctrl_stress_all.3314809125 |
|
|
May 29 01:30:19 AM PDT 23 |
May 29 01:55:28 AM PDT 23 |
4917146337 ps |
| T8 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1384058353 |
|
|
May 29 01:10:34 AM PDT 23 |
May 29 01:10:46 AM PDT 23 |
1176221262 ps |
| T82 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.3813139074 |
|
|
May 29 01:31:04 AM PDT 23 |
May 29 01:31:10 AM PDT 23 |
602837345 ps |
| T124 |
/workspace/coverage/default/9.sram_ctrl_bijection.3824481581 |
|
|
May 29 01:12:29 AM PDT 23 |
May 29 01:13:54 AM PDT 23 |
11266165865 ps |
| T100 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.475098697 |
|
|
May 29 01:31:09 AM PDT 23 |
May 29 01:34:05 AM PDT 23 |
2594322293 ps |
| T28 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1635615372 |
|
|
May 29 01:29:50 AM PDT 23 |
May 29 01:55:08 AM PDT 23 |
884417737 ps |
| T56 |
/workspace/coverage/default/18.sram_ctrl_bijection.3779946963 |
|
|
May 29 01:22:35 AM PDT 23 |
May 29 01:23:51 AM PDT 23 |
3781988513 ps |
| T17 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.3903226545 |
|
|
May 29 01:28:25 AM PDT 23 |
May 29 01:31:06 AM PDT 23 |
300084682 ps |
| T57 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3037454076 |
|
|
May 29 01:30:14 AM PDT 23 |
May 29 01:34:18 AM PDT 23 |
14687580060 ps |
| T58 |
/workspace/coverage/default/35.sram_ctrl_regwen.791963322 |
|
|
May 29 01:30:17 AM PDT 23 |
May 29 01:38:36 AM PDT 23 |
1216247492 ps |
| T27 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1430098436 |
|
|
May 29 01:17:25 AM PDT 23 |
May 29 01:17:34 AM PDT 23 |
558167382 ps |
| T59 |
/workspace/coverage/default/5.sram_ctrl_bijection.1705180383 |
|
|
May 29 01:12:41 AM PDT 23 |
May 29 01:13:04 AM PDT 23 |
1039373081 ps |
| T60 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.593199585 |
|
|
May 29 01:33:06 AM PDT 23 |
May 29 01:57:02 AM PDT 23 |
13158629083 ps |
| T61 |
/workspace/coverage/default/15.sram_ctrl_stress_all.3819749042 |
|
|
May 29 01:19:08 AM PDT 23 |
May 29 01:21:10 AM PDT 23 |
2157634634 ps |
| T43 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1148673619 |
|
|
May 29 01:31:06 AM PDT 23 |
May 29 02:01:44 AM PDT 23 |
146299756850 ps |
| T117 |
/workspace/coverage/default/23.sram_ctrl_executable.3107857763 |
|
|
May 29 01:27:31 AM PDT 23 |
May 29 01:35:28 AM PDT 23 |
44990559575 ps |
| T33 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2534808080 |
|
|
May 29 01:33:10 AM PDT 23 |
May 29 01:33:11 AM PDT 23 |
127843136 ps |
| T125 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1371771135 |
|
|
May 29 01:27:08 AM PDT 23 |
May 29 01:27:11 AM PDT 23 |
87825573 ps |
| T126 |
/workspace/coverage/default/42.sram_ctrl_executable.2733509925 |
|
|
May 29 01:31:59 AM PDT 23 |
May 29 01:38:52 AM PDT 23 |
16477377225 ps |
| T18 |
/workspace/coverage/default/14.sram_ctrl_alert_test.476967327 |
|
|
May 29 01:19:03 AM PDT 23 |
May 29 01:19:04 AM PDT 23 |
13828150 ps |
| T127 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3101378141 |
|
|
May 29 01:29:44 AM PDT 23 |
May 29 01:32:00 AM PDT 23 |
952021131 ps |
| T128 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2186071479 |
|
|
May 29 01:22:32 AM PDT 23 |
May 29 01:22:40 AM PDT 23 |
72437654 ps |
| T19 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1393115384 |
|
|
May 29 01:32:48 AM PDT 23 |
May 29 01:32:49 AM PDT 23 |
13904139 ps |
| T83 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1275114551 |
|
|
May 29 01:14:44 AM PDT 23 |
May 29 01:14:49 AM PDT 23 |
63084292 ps |
| T129 |
/workspace/coverage/default/0.sram_ctrl_bijection.3601195155 |
|
|
May 29 01:08:06 AM PDT 23 |
May 29 01:09:09 AM PDT 23 |
3829393361 ps |
| T20 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1991315480 |
|
|
May 29 01:29:39 AM PDT 23 |
May 29 01:29:40 AM PDT 23 |
32069826 ps |
| T84 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.2477677391 |
|
|
May 29 01:27:16 AM PDT 23 |
May 29 01:52:17 AM PDT 23 |
16071562778 ps |
| T130 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.4072656645 |
|
|
May 29 01:31:16 AM PDT 23 |
May 29 01:31:21 AM PDT 23 |
232901950 ps |
| T116 |
/workspace/coverage/default/33.sram_ctrl_executable.3933915090 |
|
|
May 29 01:30:11 AM PDT 23 |
May 29 01:49:56 AM PDT 23 |
3860229097 ps |
| T131 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3434250475 |
|
|
May 29 01:28:25 AM PDT 23 |
May 29 01:28:36 AM PDT 23 |
241433141 ps |
| T132 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2315543216 |
|
|
May 29 01:25:33 AM PDT 23 |
May 29 01:25:51 AM PDT 23 |
2044766974 ps |
| T133 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3423781683 |
|
|
May 29 01:12:27 AM PDT 23 |
May 29 01:12:40 AM PDT 23 |
1245944326 ps |
| T134 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.28596249 |
|
|
May 29 01:31:45 AM PDT 23 |
May 29 01:33:21 AM PDT 23 |
149656304 ps |
| T135 |
/workspace/coverage/default/30.sram_ctrl_regwen.728241450 |
|
|
May 29 01:29:19 AM PDT 23 |
May 29 01:41:30 AM PDT 23 |
35727559474 ps |
| T101 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3951316685 |
|
|
May 29 01:31:05 AM PDT 23 |
May 29 01:33:47 AM PDT 23 |
1714338667 ps |
| T136 |
/workspace/coverage/default/6.sram_ctrl_regwen.2376221390 |
|
|
May 29 01:12:26 AM PDT 23 |
May 29 01:28:53 AM PDT 23 |
4247567358 ps |
| T137 |
/workspace/coverage/default/6.sram_ctrl_bijection.1197745071 |
|
|
May 29 01:12:27 AM PDT 23 |
May 29 01:12:46 AM PDT 23 |
1069721319 ps |
| T118 |
/workspace/coverage/default/20.sram_ctrl_regwen.3089978234 |
|
|
May 29 01:25:23 AM PDT 23 |
May 29 01:44:57 AM PDT 23 |
46624472904 ps |
| T138 |
/workspace/coverage/default/5.sram_ctrl_executable.1199267302 |
|
|
May 29 01:12:29 AM PDT 23 |
May 29 01:40:55 AM PDT 23 |
16734688571 ps |
| T122 |
/workspace/coverage/default/14.sram_ctrl_executable.1501183760 |
|
|
May 29 01:19:09 AM PDT 23 |
May 29 01:34:12 AM PDT 23 |
32719565179 ps |
| T29 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2969623023 |
|
|
May 29 01:28:59 AM PDT 23 |
May 29 02:24:42 AM PDT 23 |
1444417420 ps |
| T139 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.131915775 |
|
|
May 29 01:32:29 AM PDT 23 |
May 29 01:32:38 AM PDT 23 |
269971998 ps |
| T140 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.4196931178 |
|
|
May 29 01:17:06 AM PDT 23 |
May 29 01:17:16 AM PDT 23 |
463541289 ps |
| T141 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1498690059 |
|
|
May 29 01:22:51 AM PDT 23 |
May 29 01:22:52 AM PDT 23 |
85334679 ps |
| T142 |
/workspace/coverage/default/13.sram_ctrl_stress_all.799809347 |
|
|
May 29 01:16:58 AM PDT 23 |
May 29 01:57:21 AM PDT 23 |
43196367777 ps |
| T143 |
/workspace/coverage/default/36.sram_ctrl_executable.504025764 |
|
|
May 29 01:30:11 AM PDT 23 |
May 29 01:42:10 AM PDT 23 |
26755577410 ps |
| T85 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3205745505 |
|
|
May 29 01:28:53 AM PDT 23 |
May 29 01:58:07 AM PDT 23 |
3241299940 ps |
| T109 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.2965901009 |
|
|
May 29 01:28:28 AM PDT 23 |
May 29 01:28:33 AM PDT 23 |
597318830 ps |
| T144 |
/workspace/coverage/default/26.sram_ctrl_stress_all.2552897794 |
|
|
May 29 01:29:01 AM PDT 23 |
May 29 02:21:49 AM PDT 23 |
37984957678 ps |
| T145 |
/workspace/coverage/default/4.sram_ctrl_alert_test.830546903 |
|
|
May 29 01:12:26 AM PDT 23 |
May 29 01:12:29 AM PDT 23 |
30909566 ps |
| T146 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.588464386 |
|
|
May 29 01:22:35 AM PDT 23 |
May 29 01:22:40 AM PDT 23 |
234386621 ps |
| T30 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3118761865 |
|
|
May 29 01:22:36 AM PDT 23 |
May 29 02:05:10 AM PDT 23 |
4733422970 ps |
| T102 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.1013101830 |
|
|
May 29 01:29:43 AM PDT 23 |
May 29 01:32:46 AM PDT 23 |
1946513868 ps |
| T147 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1147877833 |
|
|
May 29 01:29:38 AM PDT 23 |
May 29 01:40:38 AM PDT 23 |
45305863986 ps |
| T148 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4103085046 |
|
|
May 29 01:33:14 AM PDT 23 |
May 29 01:33:15 AM PDT 23 |
95080234 ps |
| T149 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1585617985 |
|
|
May 29 01:32:31 AM PDT 23 |
May 29 01:32:37 AM PDT 23 |
203754404 ps |
| T150 |
/workspace/coverage/default/26.sram_ctrl_alert_test.1362519458 |
|
|
May 29 01:28:58 AM PDT 23 |
May 29 01:28:59 AM PDT 23 |
14644292 ps |
| T86 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.721171692 |
|
|
May 29 01:19:00 AM PDT 23 |
May 29 01:19:05 AM PDT 23 |
66587509 ps |
| T151 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.3578224741 |
|
|
May 29 01:29:34 AM PDT 23 |
May 29 01:29:35 AM PDT 23 |
29399757 ps |
| T103 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.111009792 |
|
|
May 29 01:28:28 AM PDT 23 |
May 29 01:35:44 AM PDT 23 |
62234219171 ps |
| T152 |
/workspace/coverage/default/47.sram_ctrl_ram_cfg.638949458 |
|
|
May 29 01:33:06 AM PDT 23 |
May 29 01:33:07 AM PDT 23 |
81748224 ps |
| T119 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.458826244 |
|
|
May 29 01:17:04 AM PDT 23 |
May 29 01:22:15 AM PDT 23 |
14577126956 ps |
| T153 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.203736965 |
|
|
May 29 01:27:49 AM PDT 23 |
May 29 01:27:55 AM PDT 23 |
147009217 ps |
| T154 |
/workspace/coverage/default/49.sram_ctrl_executable.1529314911 |
|
|
May 29 01:33:16 AM PDT 23 |
May 29 01:46:52 AM PDT 23 |
9536184004 ps |
| T120 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.1725907822 |
|
|
May 29 01:28:54 AM PDT 23 |
May 29 01:28:59 AM PDT 23 |
159449321 ps |
| T155 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.267503752 |
|
|
May 29 01:31:29 AM PDT 23 |
May 29 01:31:41 AM PDT 23 |
988309644 ps |
| T156 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2497678278 |
|
|
May 29 01:14:56 AM PDT 23 |
May 29 01:14:57 AM PDT 23 |
75549732 ps |
| T157 |
/workspace/coverage/default/8.sram_ctrl_bijection.719524842 |
|
|
May 29 01:12:27 AM PDT 23 |
May 29 01:13:18 AM PDT 23 |
798183835 ps |
| T158 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.767874095 |
|
|
May 29 01:20:48 AM PDT 23 |
May 29 01:20:49 AM PDT 23 |
47244948 ps |
| T159 |
/workspace/coverage/default/4.sram_ctrl_smoke.3762621468 |
|
|
May 29 01:10:37 AM PDT 23 |
May 29 01:11:37 AM PDT 23 |
1726603654 ps |
| T160 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3673632111 |
|
|
May 29 01:20:51 AM PDT 23 |
May 29 01:20:55 AM PDT 23 |
81881936 ps |
| T121 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3266342243 |
|
|
May 29 01:08:05 AM PDT 23 |
May 29 01:14:17 AM PDT 23 |
66876265167 ps |
| T161 |
/workspace/coverage/default/8.sram_ctrl_partial_access.2624620179 |
|
|
May 29 01:12:28 AM PDT 23 |
May 29 01:13:26 AM PDT 23 |
575139971 ps |
| T162 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.3638148598 |
|
|
May 29 01:10:29 AM PDT 23 |
May 29 01:10:35 AM PDT 23 |
336726918 ps |
| T163 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2659801222 |
|
|
May 29 01:12:27 AM PDT 23 |
May 29 01:12:34 AM PDT 23 |
348426542 ps |
| T164 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1757370332 |
|
|
May 29 01:27:32 AM PDT 23 |
May 29 01:27:36 AM PDT 23 |
171458685 ps |
| T165 |
/workspace/coverage/default/7.sram_ctrl_executable.746504494 |
|
|
May 29 01:12:27 AM PDT 23 |
May 29 01:28:14 AM PDT 23 |
12529169211 ps |
| T166 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2068689751 |
|
|
May 29 01:25:33 AM PDT 23 |
May 29 01:25:50 AM PDT 23 |
931792711 ps |
| T167 |
/workspace/coverage/default/19.sram_ctrl_regwen.2633383369 |
|
|
May 29 01:22:45 AM PDT 23 |
May 29 01:28:41 AM PDT 23 |
1607866108 ps |
| T168 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1188743035 |
|
|
May 29 01:12:26 AM PDT 23 |
May 29 01:17:10 AM PDT 23 |
6995418539 ps |
| T67 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.657980462 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
83531093 ps |
| T47 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1970643980 |
|
|
May 29 12:37:14 AM PDT 23 |
May 29 12:37:16 AM PDT 23 |
200344223 ps |
| T108 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1296754160 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
135654278 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1874666624 |
|
|
May 29 12:36:41 AM PDT 23 |
May 29 12:36:42 AM PDT 23 |
65732177 ps |
| T105 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2941403686 |
|
|
May 29 12:36:51 AM PDT 23 |
May 29 12:36:52 AM PDT 23 |
15292342 ps |
| T68 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.836326408 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:57 AM PDT 23 |
796836440 ps |
| T44 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.56012002 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
287026054 ps |
| T106 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2749231277 |
|
|
May 29 12:36:49 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
131964024 ps |
| T48 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3309955606 |
|
|
May 29 12:36:32 AM PDT 23 |
May 29 12:36:33 AM PDT 23 |
140472534 ps |
| T49 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1176447434 |
|
|
May 29 12:37:25 AM PDT 23 |
May 29 12:37:26 AM PDT 23 |
112541503 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3485670542 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
83094849 ps |
| T50 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.998753126 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
63197294 ps |
| T51 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.539300999 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
29717609 ps |
| T69 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2181286179 |
|
|
May 29 12:37:24 AM PDT 23 |
May 29 12:37:25 AM PDT 23 |
25397148 ps |
| T52 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3372474384 |
|
|
May 29 12:38:08 AM PDT 23 |
May 29 12:38:11 AM PDT 23 |
33957363 ps |
| T70 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2059470530 |
|
|
May 29 12:37:11 AM PDT 23 |
May 29 12:37:15 AM PDT 23 |
1314749729 ps |
| T71 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2116296964 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
1736393582 ps |
| T72 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.636708757 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
22008237 ps |
| T45 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2108065934 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
181919257 ps |
| T73 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2146550082 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:54 AM PDT 23 |
794809310 ps |
| T74 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1315128934 |
|
|
May 29 12:36:49 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
39847640 ps |
| T75 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1418934764 |
|
|
May 29 12:36:43 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
146788851 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1042316066 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:45 AM PDT 23 |
16552808 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3257711210 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
14317058 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1906100471 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
28945277 ps |
| T46 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2460408872 |
|
|
May 29 12:36:31 AM PDT 23 |
May 29 12:36:33 AM PDT 23 |
180901929 ps |
| T79 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1826117909 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:52 AM PDT 23 |
1550116924 ps |
| T169 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1993591871 |
|
|
May 29 12:36:42 AM PDT 23 |
May 29 12:36:43 AM PDT 23 |
23552966 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1155223895 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:52 AM PDT 23 |
195171713 ps |
| T104 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2848813053 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
24151978 ps |
| T63 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.660606925 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
293760209 ps |
| T170 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2235538557 |
|
|
May 29 12:37:11 AM PDT 23 |
May 29 12:37:13 AM PDT 23 |
37946990 ps |
| T171 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1375972469 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
32303743 ps |
| T62 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.10212764 |
|
|
May 29 12:38:04 AM PDT 23 |
May 29 12:38:06 AM PDT 23 |
1422876571 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3438562308 |
|
|
May 29 12:36:32 AM PDT 23 |
May 29 12:36:36 AM PDT 23 |
433543331 ps |
| T88 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.925427905 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
23758420 ps |
| T53 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3313773751 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
254129720 ps |
| T54 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1283551326 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
794348729 ps |
| T89 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3970550929 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:53 AM PDT 23 |
2166797546 ps |
| T172 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.683025004 |
|
|
May 29 12:36:30 AM PDT 23 |
May 29 12:36:31 AM PDT 23 |
14476017 ps |
| T173 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1442816793 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:57 AM PDT 23 |
1728698752 ps |
| T55 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3939268418 |
|
|
May 29 12:37:04 AM PDT 23 |
May 29 12:37:06 AM PDT 23 |
690293890 ps |
| T64 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2384322159 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
24687017 ps |
| T174 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2739209462 |
|
|
May 29 12:36:32 AM PDT 23 |
May 29 12:36:33 AM PDT 23 |
12983940 ps |
| T110 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3470140447 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
299207935 ps |
| T175 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1872789374 |
|
|
May 29 12:37:24 AM PDT 23 |
May 29 12:37:25 AM PDT 23 |
26009469 ps |
| T65 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2286330021 |
|
|
May 29 12:37:24 AM PDT 23 |
May 29 12:37:26 AM PDT 23 |
92132789 ps |
| T176 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3401073195 |
|
|
May 29 12:36:41 AM PDT 23 |
May 29 12:36:43 AM PDT 23 |
244757377 ps |
| T66 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.97604831 |
|
|
May 29 12:36:52 AM PDT 23 |
May 29 12:36:55 AM PDT 23 |
239653817 ps |
| T177 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1278616760 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
15531243 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.370741994 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
1999548250 ps |
| T178 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1288676476 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
124918164 ps |
| T179 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.16671422 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
117929957 ps |
| T180 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2747401477 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
58064512 ps |
| T93 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3680506474 |
|
|
May 29 12:36:49 AM PDT 23 |
May 29 12:36:54 AM PDT 23 |
1037060720 ps |
| T181 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.132382375 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:45 AM PDT 23 |
17833004 ps |
| T182 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2675931932 |
|
|
May 29 12:37:11 AM PDT 23 |
May 29 12:37:18 AM PDT 23 |
564363315 ps |
| T183 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2628427220 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
188986508 ps |
| T94 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3444886953 |
|
|
May 29 12:38:07 AM PDT 23 |
May 29 12:38:08 AM PDT 23 |
12520681 ps |
| T184 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2937227469 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
36328822 ps |
| T185 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2327206768 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
887897811 ps |
| T95 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2795682835 |
|
|
May 29 12:37:14 AM PDT 23 |
May 29 12:37:18 AM PDT 23 |
403682406 ps |
| T186 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.279423195 |
|
|
May 29 12:37:18 AM PDT 23 |
May 29 12:37:19 AM PDT 23 |
86235230 ps |
| T187 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.492745637 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
95443335 ps |
| T188 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3962168722 |
|
|
May 29 12:36:49 AM PDT 23 |
May 29 12:36:59 AM PDT 23 |
399453961 ps |
| T189 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.23337443 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
27304018 ps |
| T190 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1324108161 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
20848452 ps |
| T191 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2226274975 |
|
|
May 29 12:36:49 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
60222953 ps |
| T192 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3551917768 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
15070944 ps |
| T193 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1973012966 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
114742536 ps |
| T113 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2805867026 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:51 AM PDT 23 |
325467500 ps |
| T194 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.65868020 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:52 AM PDT 23 |
236801347 ps |
| T195 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.380823849 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
290605958 ps |
| T196 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1434641452 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
29481917 ps |
| T197 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2372490307 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
350581281 ps |
| T198 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.998848574 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
19197614 ps |
| T199 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.831777658 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
27896794 ps |
| T200 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2273248839 |
|
|
May 29 12:36:49 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
33267951 ps |
| T201 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4176851077 |
|
|
May 29 12:37:24 AM PDT 23 |
May 29 12:37:26 AM PDT 23 |
104290990 ps |
| T202 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3364088710 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
37440087 ps |
| T203 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.392553808 |
|
|
May 29 12:37:04 AM PDT 23 |
May 29 12:37:09 AM PDT 23 |
139220501 ps |
| T204 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2585964284 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
68296624 ps |
| T205 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2863377500 |
|
|
May 29 12:36:33 AM PDT 23 |
May 29 12:36:34 AM PDT 23 |
18569454 ps |
| T206 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2800645218 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
17144291 ps |
| T207 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2340190426 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
13214265 ps |
| T208 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4025823346 |
|
|
May 29 12:37:24 AM PDT 23 |
May 29 12:37:29 AM PDT 23 |
793289061 ps |
| T209 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2222951499 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
165140175 ps |
| T210 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2368461407 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
24688042 ps |
| T211 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4190330140 |
|
|
May 29 12:37:24 AM PDT 23 |
May 29 12:37:27 AM PDT 23 |
97829978 ps |
| T212 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2005060517 |
|
|
May 29 12:38:08 AM PDT 23 |
May 29 12:38:09 AM PDT 23 |
56175613 ps |
| T213 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2328900036 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
154664896 ps |
| T214 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3751228254 |
|
|
May 29 12:36:54 AM PDT 23 |
May 29 12:36:55 AM PDT 23 |
90748758 ps |
| T215 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2971595805 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
113780336 ps |
| T216 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.270353769 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
104719609 ps |
| T217 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1123247551 |
|
|
May 29 12:36:41 AM PDT 23 |
May 29 12:36:42 AM PDT 23 |
18215844 ps |
| T218 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4287647889 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
60497681 ps |
| T219 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2321855942 |
|
|
May 29 12:36:31 AM PDT 23 |
May 29 12:36:34 AM PDT 23 |
65795362 ps |
| T220 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1630189214 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:54 AM PDT 23 |
1512333688 ps |
| T221 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1707882617 |
|
|
May 29 12:36:42 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
276365031 ps |
| T222 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1890677415 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
35485479 ps |
| T223 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3041040307 |
|
|
May 29 12:37:12 AM PDT 23 |
May 29 12:37:13 AM PDT 23 |
30128457 ps |
| T224 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4208093940 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
460136073 ps |
| T225 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1179768935 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:45 AM PDT 23 |
223265349 ps |
| T226 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3204634479 |
|
|
May 29 12:36:43 AM PDT 23 |
May 29 12:36:44 AM PDT 23 |
94976584 ps |
| T227 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2506645147 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
31905279 ps |
| T228 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.897819663 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
15977155 ps |
| T229 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1369274597 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
68682465 ps |
| T230 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2406643535 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
18840331 ps |
| T231 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3063007821 |
|
|
May 29 12:37:26 AM PDT 23 |
May 29 12:37:27 AM PDT 23 |
39459090 ps |
| T232 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3548239408 |
|
|
May 29 12:37:40 AM PDT 23 |
May 29 12:37:42 AM PDT 23 |
85975798 ps |
| T233 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2936644489 |
|
|
May 29 12:37:11 AM PDT 23 |
May 29 12:37:16 AM PDT 23 |
330936063 ps |
| T234 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.797743512 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
117380766 ps |
| T235 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.791932996 |
|
|
May 29 12:36:31 AM PDT 23 |
May 29 12:36:35 AM PDT 23 |
259468463 ps |
| T114 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2724575430 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
527651477 ps |
| T112 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3839309990 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
467416309 ps |
| T236 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.252302128 |
|
|
May 29 12:36:42 AM PDT 23 |
May 29 12:36:44 AM PDT 23 |
36417464 ps |
| T237 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.856433306 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
398146410 ps |
| T238 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2058582080 |
|
|
May 29 12:36:48 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
51688417 ps |
| T239 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.970743103 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
31901361 ps |
| T240 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2216129231 |
|
|
May 29 12:36:44 AM PDT 23 |
May 29 12:36:46 AM PDT 23 |
1102062377 ps |
| T241 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3236713823 |
|
|
May 29 12:36:36 AM PDT 23 |
May 29 12:36:41 AM PDT 23 |
1495846900 ps |
| T242 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.231937681 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
64375238 ps |
| T243 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3763574747 |
|
|
May 29 12:36:49 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
22261439 ps |
| T244 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3320515584 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:55 AM PDT 23 |
404764683 ps |
| T245 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.185528443 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:49 AM PDT 23 |
383171703 ps |
| T246 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4161860837 |
|
|
May 29 12:36:31 AM PDT 23 |
May 29 12:36:33 AM PDT 23 |
190069078 ps |
| T247 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1135376685 |
|
|
May 29 12:37:25 AM PDT 23 |
May 29 12:37:26 AM PDT 23 |
170232711 ps |
| T248 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.284160920 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
26836801 ps |
| T115 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1393424502 |
|
|
May 29 12:36:47 AM PDT 23 |
May 29 12:36:50 AM PDT 23 |
329002283 ps |
| T249 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1576415515 |
|
|
May 29 12:36:46 AM PDT 23 |
May 29 12:36:48 AM PDT 23 |
343135873 ps |
| T250 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2864448057 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
338718497 ps |
| T251 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.389111549 |
|
|
May 29 12:36:45 AM PDT 23 |
May 29 12:36:47 AM PDT 23 |
68621361 ps |
| T252 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3354283956 |
|
|
May 29 12:36:39 AM PDT 23 |
May 29 12:36:40 AM PDT 23 |
12655686 ps |
| T253 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2929534013 |
|
|
May 29 12:36:31 AM PDT 23 |
May 29 12:36:32 AM PDT 23 |
20930535 ps |
| T254 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1593810309 |
|
|
May 29 12:36:49 AM PDT 23 |
May 29 12:36:52 AM PDT 23 |
876950071 ps |
| T255 |
/workspace/coverage/default/49.sram_ctrl_partial_access.2558185725 |
|
|
May 29 01:33:20 AM PDT 23 |
May 29 01:33:30 AM PDT 23 |
261911477 ps |
| T256 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.620845197 |
|
|
May 29 01:31:08 AM PDT 23 |
May 29 01:31:13 AM PDT 23 |
70998105 ps |
| T257 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2294366927 |
|
|
May 29 01:22:29 AM PDT 23 |
May 29 01:28:50 AM PDT 23 |
23881487695 ps |
| T258 |
/workspace/coverage/default/40.sram_ctrl_regwen.3734213927 |
|
|
May 29 01:31:41 AM PDT 23 |
May 29 01:32:15 AM PDT 23 |
3583333004 ps |
| T259 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1050259751 |
|
|
May 29 01:27:25 AM PDT 23 |
May 29 01:27:36 AM PDT 23 |
1824014075 ps |
| T260 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.4188884230 |
|
|
May 29 01:26:58 AM PDT 23 |
May 29 01:27:09 AM PDT 23 |
774584411 ps |
| T261 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2781632620 |
|
|
May 29 01:27:24 AM PDT 23 |
May 29 01:27:25 AM PDT 23 |
31700393 ps |
| T262 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.1328057251 |
|
|
May 29 01:10:43 AM PDT 23 |
May 29 01:10:50 AM PDT 23 |
6822507562 ps |
| T263 |
/workspace/coverage/default/27.sram_ctrl_stress_all.761298957 |
|
|
May 29 01:28:58 AM PDT 23 |
May 29 01:39:07 AM PDT 23 |
39784756194 ps |
| T264 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.2883373803 |
|
|
May 29 01:32:30 AM PDT 23 |
May 29 01:37:19 AM PDT 23 |
15311184220 ps |