Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	1	15	93.75

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	1	15	93.75	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	197461900	1			T1	17578		T2	270602		T3	98304
instr_valid_dis	149291580	1			T1	17578		T2	270602		T3	98304
instr_en	19380840	1			T29	322144		T30	322144		T31	322144

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11674500	1			T29	166654		T30	166654		T31	166654
sram_ifetch_valid_disable	147936700	1			T1	17578		T2	270602		T3	98304
sram_ifetch_enable	37850700	1			T29	445094		T30	445094		T31	445094

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	197461900	1			T1	17578		T2	270602		T3	98304
hw_debug_en_valid_off	144015500	1			T1	17578		T2	270602		T3	98304
hw_debug_en_on	33210500	1			T29	412996		T30	412996		T31	412996

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	1	15	93.75	1
Automatically Generated Cross Bins	12	1	11	91.67	1
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Uncovered bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	NUMBER	STATUS
[hw_debug_en_on]	[sram_ifetch_invalid_disable]	[instr_en]	0	1	1

Covered bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	147936700	1			T1	17578		T2	270602		T3	98304
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	132248380	1			T1	17578		T2	270602		T3	98304
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9513240	1			T29	139950		T30	139950		T31	139950
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3391700	1			T29	52676		T30	52676		T31	52676
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1369300	1			T29	27386		T30	27386		T31	27386
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	757900	1			T103	15158		T104	15158		T105	15158
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6114000	1			T29	80616		T30	80616		T31	80616
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	3030800	1			T29	60616		T30	60616		T31	60616
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	6502300	1			T29	93148		T30	93148		T31	93148
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3069900	1			T29	61398		T30	61398		T31	61398
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3165100	1			T29	31750		T30	31750		T31	31750

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9109700	1			T29	182194		T30	182194		T31	182194
lc_exec_en	20594200	1			T29	239232		T30	239232		T31	239232
valid_exec_dis	145691000	1			T1	17578		T2	270602		T3	98304
invalid_exec_dis	49525200	1			T29	611748		T30	611748		T31	611748