| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.35344207087126131876085535942104836476676219653903720130087161502267037731861 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.58858551621889702820276308727602337265130006528830258127011400908844321094123 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.85477587543772301161717503353775504570907188800391731153769022184699505533068 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.91479072273175075306070035600393194863106187162924901989995271800029054899610 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.68004552515598517176285873730012749612904937691785856865985375250281683891349 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.32922490899492211048740377386708372575801231695150379238736533621097615099682 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.70972529052789942649857724977370985461302969962050019404832726849628068485887 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.17217097611709392722999442758759508812545957286593685436003930116258728363293 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.7699367062620728182965349957926331386081848309592874590431787377959916141965 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.76683178373923319445858241035133579666736679970919315042574679802308715297451 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.64276510853941309502290112967221466991394370226288981512403686340810363262725 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.22937024108480776375185664722497461971361756697455679831022104077183056920281 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.17881321297257179224929275493829327007584490127851041689026352800527392999061 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.20540568762557712705316764335195439831686808225924121824110457876173771387866 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.63837900275081450224939668424984364748994281518907393524339178267918912259895 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.55301225597065462426600121385056071557568874628244658385475871926404741238731 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.51082621758534191823475596832053963699546187025240358594442787446239885574697 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.24230074366302847188641141870498691440673437315977087525645900578284387501750 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.7736057543356939407288076230138740212595468726907831534398721850139410061204 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.70021960431785744599137763208341306972155498301520972683279592361618758649519 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.38076547875381042446787350901237567823022004888219054591361580233736925058491 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.51100835925318828865839338740187743816129544300044659281198761964949354357472 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.25535170266456198463081862051437548389045825267908035961894498427131300371571 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.113032343931052855546912603758491979437863147778081512265700264847191668053654 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.21836586940944478023012462791064583478390939789173665536173513262272315807434 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.99480986044773749480455138613678834948631220260155604595434185307691748402875 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.103612007506538836847025077029823550436906469921374645314266683869062844606745 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4387352708546492315516285356288403907189969804313283653429668542695991288623 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.101630742544515552691595586033555755317039311660940184469289387613661462905793 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.49897033721943595653417566815730997249103618714608509491791052743466660781250 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.93551197388887001014519168506317190179767117151237086738996316909420767866342 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.73695448191253724263137503358731545994436351972151025923872527451036011324383 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.18825599753572018064268589239735936383743529846490739158296365265137461760596 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.13045751856660649503020527848423223453025413990491822605324368746543727589952 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.90059446336839697186273114110426183886829809807442143705357707661965927585351 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.90818558460245025625791724583292395222448303999906859556946807444997167917498 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.82624350122360606170428538691719982108343155043264777863178543041131849273587 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.77874049004641549340748128826576162104263097216942166022604341399284091122360 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.15211662017431585364535629708835902467614254252500294838708123661185820905453 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.49256534505087259564197923704178608151190783820590900983820043443483782817306 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.108287363851949525233282096048095334682194873719609682232769984482063781932991 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.65643416318912618310359095735841338186243567193020076755603593738925666711011 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4952281565772374971364403492063121619677453345316802155191118673957273890692 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.22294918024732629444918098361867153935773056161130822463521931732998582518191 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.59665042744600541065684859679911134965175284675250136785855129836557911303087 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.100946209906833150035105828388771806891278535773644823935880487181859205223373 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.6632676054407902281624500598923414337871904708311143215904300810004289922875 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.78586549581909820618534686109347446536629475475842355247167863385393907839789 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.86793776140405380349804962695242621025578467860231218679351110454014416055608 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.80585766776139879244547785125294070702538034109677707899276212015461580218576 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.42713458726106725733624044128965830514467489613102541026401300231023683200700 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.13343786748517112141492097102901448899442007070416335946101062795258882982384 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.98365029655841680483814258931055833498605232204890498110704517979504855497174 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.107870060953486115357208480003383135328912769371980218661743960182855103324267 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.74900152034940443375455228517145841793743098805172123440607142961595195054735 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.36078525296484828726883768991909655906158929168061338682417267949849031923278 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.69789340410008118413719121965151022080863013649126365144053674210526764945686 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.39179649918412738471865900625200888079209204192908336468170868406043619592045 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.55329315694734598663475181334013306814871239446796792077829656215045239680324 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.24277553946059041994574079648469257146304958222502586918990466516895007726065 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.91097627221304618887338730079719624684597797198583968009709546570378284237156 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.35187209078562973305188023473699524581470278395362206790508749494948030322192 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.7190704105138391620292676973648826525904276986573908481804581040222611027995 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.50759051981567218529258820871050158729869386663658695554762341024464412478504 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.60648195364381642068265103469963512380757351676543998012437296067259743556540 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.94931798977536815209088238339862429778411480317236600409383817374719816370076 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.25304744869156778984002077273703143279954259253185906177654924953765359329273 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.78450693560108860370145682862155610238955982728097626319459689198986703065705 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.108106366045324679377376630169498307392023806530581927602515208833343821551411 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.33523699205170255826840903290509896875304609488642452149441176261702024192901 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.13460307893174736278521491480544455202872249865895222189998915334498267957559 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.111280950271447359915840902270051363950117758937660693331248210120567825348776 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.50868298478002042238990009199070756765420572877837268249586639266757208535063 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.85942580501429618612513271456591972090175670803830137390028762629140392573014 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.62669910071930551012923352123261333564177086043599812189776906835195186013989 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.64160278501570190306527199776494444244281014462557859675940307942228258366982 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.53180419778975071364283293831653782841260203529571507450259356556664257831644 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.100051716487575780650022725079094994464326346870175960131770326848503565094189 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.95640057402110074813327865964712316369342173334040905636566494252551596878894 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.102349189713756331358131079442395675906747499653870346972303421228342895266906 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.53633432324803528356072323311113587320942053632634015162192578828894113614914 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.99751429085359762324550072986149616624546979552585163912277138612780724798515 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.58859936774628914698744903493003146760979568234880843441778055124142550293231 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.7799886262796051734291511660442707757798024725687995963000403088678728394176 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.24050586511191575009595924559966590137989167047775248875306916224932277518340 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.72511336078264838835267305913811948868526514398123593360543743968238307266866 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.80845694221042498276157310337051289823797659341661083341507075224076969663304 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.106182215045913259645322009484090501728935375629439490979857249152051239443137 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.21640118229439219877363616122331570999554874256961973391992505770295316489899 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.32713107188382023981128645458664489758232668494015094760433659875430258864137 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.23858426251058180779394930813434412184856677952699525264910230410862585625859 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.26889952378642977356383144985300320980985792024862453531753806874008866743622 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.10462093361811655468994795252755977272324110622387823712884553035129469151170 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.21732394286800125878744038453361801069101376832758347929573463090994560991866 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.8033925667778401842906047243551842324431270901201728570436920948721699322952 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.57083606263436282980166676028534201387376253986714166928351978894845757276708 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.23628624064854758990016792227812837816431860152939784685050966417037407052026 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.93474778451182895297773937242661576864511363687139393191408742508636100894350 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.626104292125315831209195327102928935112207535075574790823985474304025829028 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.58969973353480329515814286958066324674812560451051286682482706429255090289086 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.111210369144860121794658045227355623083039400868727287079697250494112976732892 |
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| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.57313488391632244647572808924139893156423026155190141354656729664165713032870 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.31916764269661440356930809867431894549953244732369838650090498708899093002276 |
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| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.69942723639798080629715708021615230350159237451298812709067389995574076926023 |
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| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.106957958567402580378057557253322338171521885144715149095019738158883280806093 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.83413491760130699562782313817689138558399676828566439614408417985041186345874 |
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| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.28675151604462895937258019502856669953315675621985994696356394948549822384390 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.47505195566816822580491020547172797199721610283604245364732007200592733386450 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.24370843579216515922702902163989431918213337622858669242229970258834085770601 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.14703981804557102239583425229499104529573789725395596918334097324356243948692 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.29220996456221265758839240398726218984108044088738677804971015539964230107438 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1696246166583056704524131801291413612178399226332775800005543207710844718136 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.17648985734186358509472668800300882605273184405523035884879801081764024376778 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2839806213832825161358966831483789252032173554728401016141796045669979231167 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.114374424884706676693231115448081590557432780757282686099599854400923633807698 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.17048960809256976100334684237507470711898493728764594884669815066503580024518 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.9079604700174297859347022185518914214272644802222401413400694952754153652101 |
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| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.27286282361183275309104239400018827941105799442450543331764884867002760649813 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.16331368040532629229140035269798102078836892359583651510777027652395832003187 |
| /workspace/coverage/default/6.sram_ctrl_bijection.12955502644157558392889601159808174588790149191073051114837147504586807906557 |
| /workspace/coverage/default/6.sram_ctrl_executable.76062380328796112214923030446180008227110811159246449443493727617966790280849 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.99180398760928107484623878247262781129210864763208644746407766355614007495421 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.73568623885273730450079797407022815852185794254575124873183461438233075013677 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.66677470042594116491342412618619656622163038911685073864277221715324330957740 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.5911602860308587051390797758719554071899052118963352774869780093227425479028 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.115482739590792469674488242208337218723764315047443861333967333048051016566882 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.14344941421282415197790422528215028224121193866675870664768453848515694362217 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.60042177151347530424025626104193139623318635001345088993240563982260837271013 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.46349811661519030923466520701049093232803646150408893049030623872810625493188 |
| /workspace/coverage/default/6.sram_ctrl_regwen.23287645579490758580577757918325195506611203852988081883468930544590490985021 |
| /workspace/coverage/default/6.sram_ctrl_smoke.96251202528930839510132270991679513220184281661055215586190553087935650483782 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.85353275867313696514331649277214793088928481883199193947567604164033899534902 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.69555725039975662635840466722958196886000686610202195687427698735516701693085 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.23945994534801221693020966328238164409592974179898272291110653916471235008671 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.61984956891140548085685104036553521606657873918289853446968909470106954772250 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3577985479266740933981060288818564848706979753750676925402948328193646718712 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.60139267486302404347584345701951727311383026523914554390141042192333310784473 |
| /workspace/coverage/default/7.sram_ctrl_bijection.51502581011423112901533035013886948661337026809709264202672389402396979459247 |
| /workspace/coverage/default/7.sram_ctrl_executable.20600730255538537312274972644684630989954197950629537199038218661970709202227 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.35690086920799195423411771716028634578389106466563056114557304532504448769532 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.56054440429850230219861969885777422529231957066657698033705350609409608810963 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.46785526050071926686252501473361068626393592026297346737313368510419505833929 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.111072705380812467017816096858211547062269652762000376681688380981146192714278 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.101441567260920966934219090061480866242541885374583565380826672069405484972912 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.87615826307238445229021457318246765914632255424903165061602085439263363503946 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.103298420817463781585869094223277696159579205462358788583953189907559584981655 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.75055511259939642997360943085943001950782419550115774134083590549868738703030 |
| /workspace/coverage/default/7.sram_ctrl_regwen.60869041169791237175143008689949091822998257362179913883869378981309323245173 |
| /workspace/coverage/default/7.sram_ctrl_smoke.107268573615754140761536622724032000714056076761052089059788321793244923115909 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.28762069131046477770771762995492867668790573870458052888384891740867119256904 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.54885340239896699726216967193861349636818309629989751100721770713945761779266 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.31871177499736058379082866657305805841102306376816282711362344667802905502638 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.65089179359011457101718108591089154612484316963415503262935712223628793770134 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.29602726678192382767746124875642795097217082769247553132954910302336101728519 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.59827222691222097190372285528329548564319746639128950746402987611787432284471 |
| /workspace/coverage/default/8.sram_ctrl_bijection.98686981392008353745248297210266929255071303108883632248610634244548662914841 |
| /workspace/coverage/default/8.sram_ctrl_executable.88866625934449268191083501009800986405917223816995442615443825648832850346578 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.76756245338797371144832990566486157184822583058299339704916425785969918969278 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.22848753785648929318714918424684058442489122537431746941612500708547351411536 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.48934126875089417922540553653383632612435220211953626077441612815203999136370 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.66995042027691610498694193948720571694814978450567914351181149589380036268996 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.59324070730549328470587203995667987605031876589872948090160619857091363116144 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.101710250639225190176892958128075866593260691958260991560151328266123447925635 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.97527562628970611548963905447636806920108148521864427632217709385510251577659 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.12467526404756558329817018159866921215078504423238105137759917260922796437263 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1812325402132794412587679296843408336188820318250485269926193785897172315086 |
| /workspace/coverage/default/8.sram_ctrl_smoke.34010296906965006569126588179293475239342198982726440831076936284960942133789 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.948537715975402707146338349208542471066046439077034999387761379420097542125 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.17118937358109241092733380901809092314462258988126116107990354819202212377216 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.95084595706055705461805702240933894320440164539509660218682480951768243703896 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2925552119834756505644404915621110316931967523407542756676959058935247997125 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.33210275384407072045686558764764304882321970712295866243981131307577850454229 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.7072726667968742500501409844011691926441148598643720420923416940780196465207 |
| /workspace/coverage/default/9.sram_ctrl_bijection.10186150546143908710557617070074619277501012567211230231712811696727996224750 |
| /workspace/coverage/default/9.sram_ctrl_executable.38582109453829996607999299518187765971716615820972288744139397524538385864176 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.91531988655608908144651569934955147702106531841646456792646982025294648913263 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.75474279717080779415140789650802406580397231318774810176646886775920145698688 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.50518099803098011181764373573957464753765814186252096361452633223662906787723 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.11137661250705635192509490470595492533560128665407020809697260007344883440489 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.61215513863061341689039302207107177828356106798290240320758785037811078749705 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.66259496480549433744624919127382445027657773122920471507374287844260032628095 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.108622941655065597048842417336920967265473567494992297383728041028404716543678 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.29237753485018919991620075799628330353839069736796984320284839201822190954964 |
| /workspace/coverage/default/9.sram_ctrl_regwen.18638246328515846987062078399420194193206106253239173243212335044274312699231 |
| /workspace/coverage/default/9.sram_ctrl_smoke.52405322244210542872684244780245642756506570679308041845496560130761966386328 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.32561909432011009478850295973152701765742351180266636509046410101674391673069 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.53769950094295375819207509616024577470094719417416263722193460289390467052425 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.86559766893484739796543933534953085904998031979751824795342750853454956011434 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2596501180263477885895381754843758332367859132101905112730354490980657841261 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.112143713743989859011033012870695097719564174347638682913654123251446595024293 |
|
|
Nov 22 01:21:52 PM PST 23 |
Nov 22 01:23:31 PM PST 23 |
237420487 ps |
| T2 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.61789951420248180503814899596344337014834025558107815322045129422247170283698 |
|
|
Nov 22 01:22:04 PM PST 23 |
Nov 22 01:36:04 PM PST 23 |
21947461091 ps |
| T3 |
/workspace/coverage/default/5.sram_ctrl_bijection.98155339026202853486163859420552546153574267972043196309795383887634300850974 |
|
|
Nov 22 01:21:10 PM PST 23 |
Nov 22 01:22:34 PM PST 23 |
9249473390 ps |
| T4 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.4730286989779124310790305643566194536677240214385341487936215427795392778648 |
|
|
Nov 22 01:22:25 PM PST 23 |
Nov 22 01:28:27 PM PST 23 |
6491370455 ps |
| T5 |
/workspace/coverage/default/20.sram_ctrl_partial_access.12172085112120321244838645807896127395131617079037303900523599671150426851106 |
|
|
Nov 22 01:21:58 PM PST 23 |
Nov 22 01:22:17 PM PST 23 |
445204539 ps |
| T9 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.58041269111263173602035132205774936985529583341179463634931855796375552631540 |
|
|
Nov 22 01:21:51 PM PST 23 |
Nov 22 01:41:35 PM PST 23 |
624328106 ps |
| T10 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.111072705380812467017816096858211547062269652762000376681688380981146192714278 |
|
|
Nov 22 01:21:26 PM PST 23 |
Nov 22 01:21:41 PM PST 23 |
590810517 ps |
| T11 |
/workspace/coverage/default/39.sram_ctrl_bijection.105531592090625840266323253791953001084128982181281701356639021459182138852730 |
|
|
Nov 22 01:22:55 PM PST 23 |
Nov 22 01:24:28 PM PST 23 |
9249473390 ps |
| T12 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.115482739590792469674488242208337218723764315047443861333967333048051016566882 |
|
|
Nov 22 01:21:23 PM PST 23 |
Nov 22 01:37:51 PM PST 23 |
21947461091 ps |
| T13 |
/workspace/coverage/default/30.sram_ctrl_smoke.30225773853225428726493512982221888225768401267029482574133331795931875374599 |
|
|
Nov 22 01:22:07 PM PST 23 |
Nov 22 01:22:21 PM PST 23 |
427865392 ps |
| T6 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.60045879587160768985927629605426237556494197672234785830979156816792445551220 |
|
|
Nov 22 01:21:10 PM PST 23 |
Nov 22 01:21:19 PM PST 23 |
985753786 ps |
| T14 |
/workspace/coverage/default/31.sram_ctrl_partial_access.99612169851617651241484630015006931101874383736797794821984665451481882486160 |
|
|
Nov 22 01:22:28 PM PST 23 |
Nov 22 01:22:47 PM PST 23 |
445204539 ps |
| T15 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.32631246427085174073686477193781337387315092135184159500933604996787251059138 |
|
|
Nov 22 01:21:44 PM PST 23 |
Nov 22 01:28:00 PM PST 23 |
6491370455 ps |
| T16 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.76220056386358724486211285565857037960614098654797564025073275187612662943837 |
|
|
Nov 22 01:23:02 PM PST 23 |
Nov 22 01:45:16 PM PST 23 |
624328106 ps |
| T57 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.108003257046311806485875182055049267156693994753698146655033961389178618100454 |
|
|
Nov 22 01:23:12 PM PST 23 |
Nov 22 01:23:23 PM PST 23 |
166171057 ps |
| T68 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.21229173386004056760287564690110312428490189432505177886667654133585569260096 |
|
|
Nov 22 01:20:52 PM PST 23 |
Nov 22 01:21:02 PM PST 23 |
590810517 ps |
| T69 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.7085468572106307587970087018408426773240761767889266961049037800559352489796 |
|
|
Nov 22 01:21:32 PM PST 23 |
Nov 22 01:23:10 PM PST 23 |
237420487 ps |
| T17 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.18742152825620717125140258077422983296474771098036421286222804918739620709298 |
|
|
Nov 22 01:21:50 PM PST 23 |
Nov 22 01:41:06 PM PST 23 |
624328106 ps |
| T66 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.60596284763876425057843826164363179800950453798668294375762457707170657766338 |
|
|
Nov 22 01:21:54 PM PST 23 |
Nov 22 01:30:50 PM PST 23 |
42305619653 ps |
| T70 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.92230461474630756704872839486050080274745421273963753806409216693576713039293 |
|
|
Nov 22 01:22:07 PM PST 23 |
Nov 22 01:31:08 PM PST 23 |
42305619653 ps |
| T29 |
/workspace/coverage/default/38.sram_ctrl_stress_all.76726527580172217618791812908426891607929464264584408294629745670964042896504 |
|
|
Nov 22 01:22:34 PM PST 23 |
Nov 22 02:11:37 PM PST 23 |
121463254244 ps |
| T48 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1828985353508639838636560758326309364327849460923219764295413009056989881663 |
|
|
Nov 22 01:22:12 PM PST 23 |
Nov 22 01:42:44 PM PST 23 |
624328106 ps |
| T32 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.78577192482608619299019951286858713886141442289037841719885389170825104050255 |
|
|
Nov 22 01:22:43 PM PST 23 |
Nov 22 01:22:51 PM PST 23 |
40672061 ps |
| T106 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.115630001725409125248502478286125448541958504942844605329334289206543387821548 |
|
|
Nov 22 01:23:03 PM PST 23 |
Nov 22 01:24:52 PM PST 23 |
237420487 ps |
| T107 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.3695186736745291917591193907881032441571415887874615391691883095563508857402 |
|
|
Nov 22 01:22:30 PM PST 23 |
Nov 22 01:22:41 PM PST 23 |
590810517 ps |
| T108 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.101470002379162524497357640670982288755648402880514278613236291468810426779078 |
|
|
Nov 22 01:23:08 PM PST 23 |
Nov 22 01:23:24 PM PST 23 |
590810517 ps |
| T18 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.33210275384407072045686558764764304882321970712295866243981131307577850454229 |
|
|
Nov 22 01:21:28 PM PST 23 |
Nov 22 01:32:07 PM PST 23 |
4471404472 ps |
| T30 |
/workspace/coverage/default/26.sram_ctrl_stress_all.12607617627645419091746244395734214693589389022675674010014643040958630191836 |
|
|
Nov 22 01:23:25 PM PST 23 |
Nov 22 02:14:42 PM PST 23 |
121463254244 ps |
| T71 |
/workspace/coverage/default/6.sram_ctrl_bijection.12955502644157558392889601159808174588790149191073051114837147504586807906557 |
|
|
Nov 22 01:21:20 PM PST 23 |
Nov 22 01:22:49 PM PST 23 |
9249473390 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_stress_all.15310263608153630895258250638502633789395170658816139124134620233555096077883 |
|
|
Nov 22 01:21:11 PM PST 23 |
Nov 22 02:22:19 PM PST 23 |
121463254244 ps |
| T19 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.101165950704738646122004329435129578647005313818326142199825151807833336400878 |
|
|
Nov 22 01:23:26 PM PST 23 |
Nov 22 01:36:33 PM PST 23 |
4471404472 ps |
| T76 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.6137601794967240670567620432428017158290624788464938432436789643616453347761 |
|
|
Nov 22 01:24:12 PM PST 23 |
Nov 22 01:24:18 PM PST 23 |
166171057 ps |
| T77 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.39415071113318390485594695358111428985223224253251700154616898348486725314936 |
|
|
Nov 22 01:22:53 PM PST 23 |
Nov 22 01:23:10 PM PST 23 |
166171057 ps |
| T109 |
/workspace/coverage/default/34.sram_ctrl_stress_all.92744116103353450062971321839681899922454455333280157711181240589892396509829 |
|
|
Nov 22 01:22:32 PM PST 23 |
Nov 22 02:16:07 PM PST 23 |
121463254244 ps |
| T91 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.55680301074800501304394191407986437043839195336904758794029590172882115515934 |
|
|
Nov 22 01:22:35 PM PST 23 |
Nov 22 01:28:43 PM PST 23 |
6491370455 ps |
| T99 |
/workspace/coverage/default/7.sram_ctrl_regwen.60869041169791237175143008689949091822998257362179913883869378981309323245173 |
|
|
Nov 22 01:21:15 PM PST 23 |
Nov 22 01:31:18 PM PST 23 |
19383553031 ps |
| T110 |
/workspace/coverage/default/37.sram_ctrl_bijection.6607441549656539800362330400437994088687178759070815914651382173717240780521 |
|
|
Nov 22 01:22:44 PM PST 23 |
Nov 22 01:24:14 PM PST 23 |
9249473390 ps |
| T33 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.88023063000885308863248325642619401135304416976092243271710608800942355109451 |
|
|
Nov 22 01:22:31 PM PST 23 |
Nov 22 01:22:37 PM PST 23 |
40672061 ps |
| T103 |
/workspace/coverage/default/38.sram_ctrl_executable.28913992269283784047031689626012070282226603651582791167923823898251922461434 |
|
|
Nov 22 01:22:58 PM PST 23 |
Nov 22 01:34:54 PM PST 23 |
23162112088 ps |
| T111 |
/workspace/coverage/default/47.sram_ctrl_stress_all.76778083912144972194590106364474929162787023948829956545723159901914600890374 |
|
|
Nov 22 01:23:10 PM PST 23 |
Nov 22 02:17:43 PM PST 23 |
121463254244 ps |
| T100 |
/workspace/coverage/default/1.sram_ctrl_regwen.78486342165084766254364803923343521716211054588174865349805454906242608783702 |
|
|
Nov 22 01:21:07 PM PST 23 |
Nov 22 01:29:51 PM PST 23 |
19383553031 ps |
| T92 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.64001526337935721462561958768208278722373215825362015279288846433018213296601 |
|
|
Nov 22 01:21:25 PM PST 23 |
Nov 22 01:30:36 PM PST 23 |
42305619653 ps |
| T93 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.38911795029532664793361650179383120055424379261461432949663163640164016994897 |
|
|
Nov 22 01:21:38 PM PST 23 |
Nov 22 01:30:41 PM PST 23 |
42305619653 ps |
| T104 |
/workspace/coverage/default/47.sram_ctrl_executable.76776406032571805886817522028635662052253706475836054284690518407665176583823 |
|
|
Nov 22 01:23:23 PM PST 23 |
Nov 22 01:37:13 PM PST 23 |
23162112088 ps |
| T112 |
/workspace/coverage/default/45.sram_ctrl_smoke.40316089123269444379182959529725229271576133879042724160023792528882998335003 |
|
|
Nov 22 01:22:50 PM PST 23 |
Nov 22 01:23:17 PM PST 23 |
427865392 ps |
| T21 |
/workspace/coverage/default/16.sram_ctrl_alert_test.94144587954022426040774526627949975339617599036768096835714585916430440076105 |
|
|
Nov 22 01:21:45 PM PST 23 |
Nov 22 01:21:51 PM PST 23 |
16600825 ps |
| T94 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.71975708857813270318076952666631986990487965885374242689231707803081212711645 |
|
|
Nov 22 01:20:57 PM PST 23 |
Nov 22 01:27:01 PM PST 23 |
6491370455 ps |
| T113 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.81039114653423355767104946535458790486933750599040150146492876267642836805302 |
|
|
Nov 22 01:23:08 PM PST 23 |
Nov 22 01:24:44 PM PST 23 |
209242141 ps |
| T114 |
/workspace/coverage/default/30.sram_ctrl_bijection.66209698887082511809704356090624787733562885592663455565796702218232319511791 |
|
|
Nov 22 01:22:08 PM PST 23 |
Nov 22 01:23:35 PM PST 23 |
9249473390 ps |
| T115 |
/workspace/coverage/default/29.sram_ctrl_stress_all.44954429478169682118941313980481568007470133151353676984022902554051383307967 |
|
|
Nov 22 01:22:22 PM PST 23 |
Nov 22 02:27:11 PM PST 23 |
121463254244 ps |
| T116 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.111428404433508888562996370429156779091721669206766217863666941816475878194216 |
|
|
Nov 22 01:23:09 PM PST 23 |
Nov 22 01:24:37 PM PST 23 |
237420487 ps |
| T105 |
/workspace/coverage/default/13.sram_ctrl_executable.2694422976414111949966599320350913487708001951176535173087310513701881384822 |
|
|
Nov 22 01:22:25 PM PST 23 |
Nov 22 01:33:48 PM PST 23 |
23162112088 ps |
| T117 |
/workspace/coverage/default/44.sram_ctrl_executable.60161730893757277022566072949754072458428812346973525613918226329077328500372 |
|
|
Nov 22 01:22:43 PM PST 23 |
Nov 22 01:33:29 PM PST 23 |
23162112088 ps |
| T118 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.111720747883655502581594112230197452023152295797288537532160774457926873968395 |
|
|
Nov 22 01:23:05 PM PST 23 |
Nov 22 01:23:21 PM PST 23 |
590810517 ps |
| T119 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.112362349929923883263202478061372884857655688014381090851465920144363270322518 |
|
|
Nov 22 01:20:49 PM PST 23 |
Nov 22 01:30:33 PM PST 23 |
21947461091 ps |
| T120 |
/workspace/coverage/default/9.sram_ctrl_stress_all.32561909432011009478850295973152701765742351180266636509046410101674391673069 |
|
|
Nov 22 01:21:19 PM PST 23 |
Nov 22 02:20:16 PM PST 23 |
121463254244 ps |
| T34 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.59552647376619705122685392823707360179197178579893463325515741461946964900892 |
|
|
Nov 22 01:21:53 PM PST 23 |
Nov 22 01:21:59 PM PST 23 |
40672061 ps |
| T121 |
/workspace/coverage/default/40.sram_ctrl_executable.9634169939423743493074083623446345619414124693461977897247276713260867818759 |
|
|
Nov 22 01:22:35 PM PST 23 |
Nov 22 01:35:30 PM PST 23 |
23162112088 ps |
| T122 |
/workspace/coverage/default/29.sram_ctrl_executable.96287018328772306924553169795680313797215616659710831250540640238886812430188 |
|
|
Nov 22 01:22:13 PM PST 23 |
Nov 22 01:41:09 PM PST 23 |
23162112088 ps |
| T20 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.4132949025176941701272314596387321491392695583618590469949765278528663671671 |
|
|
Nov 22 01:23:49 PM PST 23 |
Nov 22 01:34:47 PM PST 23 |
4471404472 ps |
| T123 |
/workspace/coverage/default/42.sram_ctrl_stress_all.48376231920435186849904540959579573517837741670123115714646237679496333462067 |
|
|
Nov 22 01:23:07 PM PST 23 |
Nov 22 02:23:10 PM PST 23 |
121463254244 ps |
| T7 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.91531988655608908144651569934955147702106531841646456792646982025294648913263 |
|
|
Nov 22 01:21:31 PM PST 23 |
Nov 22 01:21:45 PM PST 23 |
985753786 ps |
| T124 |
/workspace/coverage/default/23.sram_ctrl_executable.69017219523143160810153691403483047891435463566528334322154292666241483331984 |
|
|
Nov 22 01:22:45 PM PST 23 |
Nov 22 01:37:00 PM PST 23 |
23162112088 ps |
| T8 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.48572021091987116086387555116672762827187975751597049944173503186855543416336 |
|
|
Nov 22 01:23:22 PM PST 23 |
Nov 22 01:23:40 PM PST 23 |
985753786 ps |
| T125 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.65839069170430406076086421863895516198044992949595365279837878364467745564325 |
|
|
Nov 22 01:22:40 PM PST 23 |
Nov 22 01:34:04 PM PST 23 |
21947461091 ps |
| T95 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.14967550270344648787872115329067498560188161836994015441741056439677723344553 |
|
|
Nov 22 01:21:13 PM PST 23 |
Nov 22 01:27:10 PM PST 23 |
6491370455 ps |
| T126 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.55377621655837192092038021956546150825788861748313678562550196139649939864261 |
|
|
Nov 22 01:20:47 PM PST 23 |
Nov 22 01:22:11 PM PST 23 |
237420487 ps |
| T78 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.111752112965823221019648180746892051141437160238632699910621944190893099832236 |
|
|
Nov 22 01:22:32 PM PST 23 |
Nov 22 01:36:00 PM PST 23 |
4471404472 ps |
| T79 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.104857521467123605864724159553621512227171584080889866781953672520002456720364 |
|
|
Nov 22 01:22:55 PM PST 23 |
Nov 22 01:34:08 PM PST 23 |
4471404472 ps |
| T96 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.93834228443060382154172212107754152910248421328982303265047271474350027926400 |
|
|
Nov 22 01:23:11 PM PST 23 |
Nov 22 01:32:17 PM PST 23 |
42305619653 ps |
| T127 |
/workspace/coverage/default/28.sram_ctrl_partial_access.29648555928088584321704118021679278934436693380971047907186429514118704015658 |
|
|
Nov 22 01:22:14 PM PST 23 |
Nov 22 01:22:29 PM PST 23 |
445204539 ps |
| T128 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.30201867043403265150899502682253146037958117524374870490165214691148645637309 |
|
|
Nov 22 01:23:13 PM PST 23 |
Nov 22 01:29:03 PM PST 23 |
6491370455 ps |
| T101 |
/workspace/coverage/default/22.sram_ctrl_regwen.24373593290285335485804482932245070834323301713396040386009110963185584381868 |
|
|
Nov 22 01:21:53 PM PST 23 |
Nov 22 01:31:54 PM PST 23 |
19383553031 ps |
| T129 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.112453491784373488818279515682763033175080958816564734133499355161745020328539 |
|
|
Nov 22 01:22:47 PM PST 23 |
Nov 22 01:24:35 PM PST 23 |
237420487 ps |
| T130 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.19440191093434778619377624670869087643226761747047639525390511014892691561156 |
|
|
Nov 22 01:22:31 PM PST 23 |
Nov 22 01:35:35 PM PST 23 |
21947461091 ps |
| T49 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.113165107112381082210067274309672067472244957002143286821569810990311565313102 |
|
|
Nov 22 01:21:31 PM PST 23 |
Nov 22 01:45:44 PM PST 23 |
624328106 ps |
| T131 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.100004758865317015440791377602550780221685082074805937629889746180717376239421 |
|
|
Nov 22 01:21:45 PM PST 23 |
Nov 22 01:23:20 PM PST 23 |
237420487 ps |
| T132 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.75148722955087650989014049119775823749217636236003368704917042256898194187212 |
|
|
Nov 22 01:22:42 PM PST 23 |
Nov 22 01:28:38 PM PST 23 |
6491370455 ps |
| T22 |
/workspace/coverage/default/5.sram_ctrl_alert_test.112165699865862534636207928440458658688379012968476702486608029963611133411967 |
|
|
Nov 22 01:21:24 PM PST 23 |
Nov 22 01:21:34 PM PST 23 |
16600825 ps |
| T80 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.83061103824926915966961457663259795137968081326522290766550154086773983334497 |
|
|
Nov 22 01:20:51 PM PST 23 |
Nov 22 01:20:59 PM PST 23 |
166171057 ps |
| T133 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.47089482314085837834927337148067265204741201656980449045224425306678883519790 |
|
|
Nov 22 01:24:13 PM PST 23 |
Nov 22 01:24:22 PM PST 23 |
590810517 ps |
| T134 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.81494504121456117192905829003175215915444263994496856060528853521568059949528 |
|
|
Nov 22 01:21:39 PM PST 23 |
Nov 22 01:36:47 PM PST 23 |
21947461091 ps |
| T81 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.50518099803098011181764373573957464753765814186252096361452633223662906787723 |
|
|
Nov 22 01:21:23 PM PST 23 |
Nov 22 01:21:35 PM PST 23 |
166171057 ps |
| T135 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.31897856240368533464266675938247745637738164040022529278456341882327756625673 |
|
|
Nov 22 01:22:21 PM PST 23 |
Nov 22 01:22:28 PM PST 23 |
590810517 ps |
| T136 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.86947706303331933530346040589280890027896678113172788419395830629720547453973 |
|
|
Nov 22 01:21:42 PM PST 23 |
Nov 22 01:21:53 PM PST 23 |
590810517 ps |
| T137 |
/workspace/coverage/default/2.sram_ctrl_smoke.5276619532238468980862459131470326965737696341235931257528563046001057833271 |
|
|
Nov 22 01:21:49 PM PST 23 |
Nov 22 01:22:06 PM PST 23 |
427865392 ps |
| T138 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.96506386336275148225086980411331510781253452789678304741120866225784306370711 |
|
|
Nov 22 01:22:52 PM PST 23 |
Nov 22 01:32:09 PM PST 23 |
42305619653 ps |
| T139 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.13924615036190669072907888429593199946704472719776065087602016433715898161589 |
|
|
Nov 22 01:21:52 PM PST 23 |
Nov 22 01:24:00 PM PST 23 |
237420487 ps |
| T140 |
/workspace/coverage/default/41.sram_ctrl_smoke.94497412813441802338128813288486868258027172624311757809600723165039252110587 |
|
|
Nov 22 01:22:34 PM PST 23 |
Nov 22 01:22:52 PM PST 23 |
427865392 ps |
| T23 |
/workspace/coverage/default/23.sram_ctrl_alert_test.24576796542352142606933617204540553271988327042209760082576666622016759363595 |
|
|
Nov 22 01:22:38 PM PST 23 |
Nov 22 01:22:44 PM PST 23 |
16600825 ps |
| T141 |
/workspace/coverage/default/1.sram_ctrl_alert_test.92536050078508482800888807922858104493572145598988197092959547932662646363543 |
|
|
Nov 22 01:21:32 PM PST 23 |
Nov 22 01:21:39 PM PST 23 |
16600825 ps |
| T142 |
/workspace/coverage/default/47.sram_ctrl_alert_test.8217109120961752422090226494787066721400113401703992613746052862258763501709 |
|
|
Nov 22 01:23:13 PM PST 23 |
Nov 22 01:23:21 PM PST 23 |
16600825 ps |
| T143 |
/workspace/coverage/default/38.sram_ctrl_smoke.62095490806496010839082136642227731137058881656881664131240705264076656778959 |
|
|
Nov 22 01:23:07 PM PST 23 |
Nov 22 01:23:29 PM PST 23 |
427865392 ps |
| T144 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.51637838686432947917744620621324318388394414264860535499659512638772464896279 |
|
|
Nov 22 01:22:54 PM PST 23 |
Nov 22 01:23:12 PM PST 23 |
590810517 ps |
| T145 |
/workspace/coverage/default/6.sram_ctrl_executable.76062380328796112214923030446180008227110811159246449443493727617966790280849 |
|
|
Nov 22 01:21:05 PM PST 23 |
Nov 22 01:37:05 PM PST 23 |
23162112088 ps |
| T146 |
/workspace/coverage/default/45.sram_ctrl_executable.23573056974758635265702850807907269014011918817980634094544997971286058630763 |
|
|
Nov 22 01:22:55 PM PST 23 |
Nov 22 01:36:36 PM PST 23 |
23162112088 ps |
| T147 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.26615849542336070826525820066739816012294193591051192209360664806920953339069 |
|
|
Nov 22 01:21:49 PM PST 23 |
Nov 22 01:33:59 PM PST 23 |
21947461091 ps |
| T148 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.73351094351514731781885578376732813497002593415056181247456300403400741725557 |
|
|
Nov 22 01:23:23 PM PST 23 |
Nov 22 01:23:35 PM PST 23 |
40672061 ps |
| T149 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.96036441755424018058437999470012837616005994324685580336147077178635003502039 |
|
|
Nov 22 01:23:17 PM PST 23 |
Nov 22 01:29:10 PM PST 23 |
6491370455 ps |
| T150 |
/workspace/coverage/default/34.sram_ctrl_partial_access.52433966414737516580767683778943899571776501980585084027828815698700330499300 |
|
|
Nov 22 01:22:45 PM PST 23 |
Nov 22 01:23:08 PM PST 23 |
445204539 ps |
| T151 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.11885217821509622867775364234116838898053191869050459548854479035327287785448 |
|
|
Nov 22 01:23:08 PM PST 23 |
Nov 22 01:24:36 PM PST 23 |
209242141 ps |
| T152 |
/workspace/coverage/default/34.sram_ctrl_regwen.31807621435651125834722439861106135366215431055911163163631542214316909816602 |
|
|
Nov 22 01:22:32 PM PST 23 |
Nov 22 01:32:37 PM PST 23 |
19383553031 ps |
| T153 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.28086931277205972209792860367983170074763157194299703945729890989858029521950 |
|
|
Nov 22 01:21:16 PM PST 23 |
Nov 22 01:21:21 PM PST 23 |
166171057 ps |
| T24 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.55983411729176806502455630785210082049545572347247520691748698980290293625625 |
|
|
Nov 22 01:20:51 PM PST 23 |
Nov 22 01:20:58 PM PST 23 |
216402798 ps |
| T37 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.5934613262540088837714206057360645575349261051618831333953883031342298632455 |
|
|
Nov 22 01:23:09 PM PST 23 |
Nov 22 01:37:05 PM PST 23 |
4471404472 ps |
| T27 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.68167615268811460100428819532594057331999668096690227688706183187060065636988 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:51 PM PST 23 |
362187346 ps |
| T50 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2839806213832825161358966831483789252032173554728401016141796045669979231167 |
|
|
Nov 22 01:19:51 PM PST 23 |
Nov 22 01:19:57 PM PST 23 |
117100021 ps |
| T28 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.35187209078562973305188023473699524581470278395362206790508749494948030322192 |
|
|
Nov 22 01:19:55 PM PST 23 |
Nov 22 01:20:00 PM PST 23 |
23886481 ps |
| T45 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.86793776140405380349804962695242621025578467860231218679351110454014416055608 |
|
|
Nov 22 01:20:30 PM PST 23 |
Nov 22 01:20:39 PM PST 23 |
362187346 ps |
| T46 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.105861264971836690020339957343268083172882015463530050502744729721408938984988 |
|
|
Nov 22 01:19:35 PM PST 23 |
Nov 22 01:19:42 PM PST 23 |
163313937 ps |
| T51 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.83413491760130699562782313817689138558399676828566439614408417985041186345874 |
|
|
Nov 22 01:20:15 PM PST 23 |
Nov 22 01:20:17 PM PST 23 |
42439904 ps |
| T98 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.80845694221042498276157310337051289823797659341661083341507075224076969663304 |
|
|
Nov 22 01:19:43 PM PST 23 |
Nov 22 01:19:50 PM PST 23 |
122117838 ps |
| T59 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.72502567380272654881013522069965146751478717453616474846321090254846015083960 |
|
|
Nov 22 01:19:47 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
19547230 ps |
| T52 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.98365029655841680483814258931055833498605232204890498110704517979504855497174 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
42439904 ps |
| T53 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.59665042744600541065684859679911134965175284675250136785855129836557911303087 |
|
|
Nov 22 01:19:38 PM PST 23 |
Nov 22 01:19:47 PM PST 23 |
117100021 ps |
| T60 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.106182215045913259645322009484090501728935375629439490979857249152051239443137 |
|
|
Nov 22 01:19:33 PM PST 23 |
Nov 22 01:19:38 PM PST 23 |
23779339 ps |
| T58 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.25535170266456198463081862051437548389045825267908035961894498427131300371571 |
|
|
Nov 22 01:19:46 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
42439904 ps |
| T154 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.102349189713756331358131079442395675906747499653870346972303421228342895266906 |
|
|
Nov 22 01:19:37 PM PST 23 |
Nov 22 01:19:45 PM PST 23 |
42439904 ps |
| T54 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.17217097611709392722999442758759508812545957286593685436003930116258728363293 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:56 PM PST 23 |
117100021 ps |
| T61 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.18716060142495409737566430933026701520618836480064421868332228477369656965940 |
|
|
Nov 22 01:19:49 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
23886481 ps |
| T47 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.106957958567402580378057557253322338171521885144715149095019738158883280806093 |
|
|
Nov 22 01:20:04 PM PST 23 |
Nov 22 01:20:07 PM PST 23 |
163313937 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.6564553950016888280673923475027132074337206502856219140905683145381489323901 |
|
|
Nov 22 01:19:51 PM PST 23 |
Nov 22 01:19:57 PM PST 23 |
163313937 ps |
| T62 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.85477587543772301161717503353775504570907188800391731153769022184699505533068 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
23779339 ps |
| T63 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.90059446336839697186273114110426183886829809807442143705357707661965927585351 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
42439904 ps |
| T64 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.93551197388887001014519168506317190179767117151237086738996316909420767866342 |
|
|
Nov 22 01:19:34 PM PST 23 |
Nov 22 01:19:42 PM PST 23 |
362187346 ps |
| T65 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.25304744869156778984002077273703143279954259253185906177654924953765359329273 |
|
|
Nov 22 01:19:54 PM PST 23 |
Nov 22 01:20:02 PM PST 23 |
362187346 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.93474778451182895297773937242661576864511363687139393191408742508636100894350 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
42439904 ps |
| T67 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.8033925667778401842906047243551842324431270901201728570436920948721699322952 |
|
|
Nov 22 01:19:45 PM PST 23 |
Nov 22 01:19:51 PM PST 23 |
22582920 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.26889952378642977356383144985300320980985792024862453531753806874008866743622 |
|
|
Nov 22 01:19:41 PM PST 23 |
Nov 22 01:19:48 PM PST 23 |
23886481 ps |
| T74 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.17881321297257179224929275493829327007584490127851041689026352800527392999061 |
|
|
Nov 22 01:19:35 PM PST 23 |
Nov 22 01:19:42 PM PST 23 |
42439904 ps |
| T75 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.80585766776139879244547785125294070702538034109677707899276212015461580218576 |
|
|
Nov 22 01:20:34 PM PST 23 |
Nov 22 01:20:39 PM PST 23 |
23886481 ps |
| T82 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.48524306730817817944516454866364573553210036923141126819382376293211297360530 |
|
|
Nov 22 01:19:54 PM PST 23 |
Nov 22 01:20:01 PM PST 23 |
362187346 ps |
| T155 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.64276510853941309502290112967221466991394370226288981512403686340810363262725 |
|
|
Nov 22 01:19:55 PM PST 23 |
Nov 22 01:20:01 PM PST 23 |
122117838 ps |
| T83 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.32713107188382023981128645458664489758232668494015094760433659875430258864137 |
|
|
Nov 22 01:20:26 PM PST 23 |
Nov 22 01:20:32 PM PST 23 |
19547230 ps |
| T55 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.62669910071930551012923352123261333564177086043599812189776906835195186013989 |
|
|
Nov 22 01:20:03 PM PST 23 |
Nov 22 01:20:07 PM PST 23 |
117100021 ps |
| T97 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.36078525296484828726883768991909655906158929168061338682417267949849031923278 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
23886481 ps |
| T84 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.29220996456221265758839240398726218984108044088738677804971015539964230107438 |
|
|
Nov 22 01:19:54 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
19547230 ps |
| T56 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.69789340410008118413719121965151022080863013649126365144053674210526764945686 |
|
|
Nov 22 01:19:51 PM PST 23 |
Nov 22 01:19:57 PM PST 23 |
117100021 ps |
| T156 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.13575901262756486693475263335955232307713430700163133913953506075160308509105 |
|
|
Nov 22 01:20:34 PM PST 23 |
Nov 22 01:20:41 PM PST 23 |
117100021 ps |
| T157 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.51100835925318828865839338740187743816129544300044659281198761964949354357472 |
|
|
Nov 22 01:19:34 PM PST 23 |
Nov 22 01:19:41 PM PST 23 |
117100021 ps |
| T158 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.67264480903026655255466949596630840545447085453312986157208223342994958119851 |
|
|
Nov 22 01:20:34 PM PST 23 |
Nov 22 01:20:40 PM PST 23 |
163313937 ps |
| T159 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.58859936774628914698744903493003146760979568234880843441778055124142550293231 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:49 PM PST 23 |
23886481 ps |
| T85 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1696246166583056704524131801291413612178399226332775800005543207710844718136 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:57 PM PST 23 |
362187346 ps |
| T160 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.21732394286800125878744038453361801069101376832758347929573463090994560991866 |
|
|
Nov 22 01:20:25 PM PST 23 |
Nov 22 01:20:31 PM PST 23 |
163313937 ps |
| T161 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.114374424884706676693231115448081590557432780757282686099599854400923633807698 |
|
|
Nov 22 01:19:53 PM PST 23 |
Nov 22 01:20:00 PM PST 23 |
163313937 ps |
| T162 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.99480986044773749480455138613678834948631220260155604595434185307691748402875 |
|
|
Nov 22 01:19:40 PM PST 23 |
Nov 22 01:19:46 PM PST 23 |
23886481 ps |
| T86 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.94931798977536815209088238339862429778411480317236600409383817374719816370076 |
|
|
Nov 22 01:19:54 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
19547230 ps |
| T163 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.107870060953486115357208480003383135328912769371980218661743960182855103324267 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
19547230 ps |
| T164 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.42713458726106725733624044128965830514467489613102541026401300231023683200700 |
|
|
Nov 22 01:19:52 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
117100021 ps |
| T165 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.100051716487575780650022725079094994464326346870175960131770326848503565094189 |
|
|
Nov 22 01:19:36 PM PST 23 |
Nov 22 01:19:43 PM PST 23 |
122117838 ps |
| T166 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.626104292125315831209195327102928935112207535075574790823985474304025829028 |
|
|
Nov 22 01:19:39 PM PST 23 |
Nov 22 01:19:46 PM PST 23 |
19547230 ps |
| T167 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.55329315694734598663475181334013306814871239446796792077829656215045239680324 |
|
|
Nov 22 01:19:55 PM PST 23 |
Nov 22 01:20:00 PM PST 23 |
42439904 ps |
| T168 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.15211662017431585364535629708835902467614254252500294838708123661185820905453 |
|
|
Nov 22 01:19:53 PM PST 23 |
Nov 22 01:20:00 PM PST 23 |
117100021 ps |
| T169 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.57313488391632244647572808924139893156423026155190141354656729664165713032870 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:50 PM PST 23 |
163313937 ps |
| T170 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.53180419778975071364283293831653782841260203529571507450259356556664257831644 |
|
|
Nov 22 01:19:34 PM PST 23 |
Nov 22 01:19:38 PM PST 23 |
22582920 ps |
| T171 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.9079604700174297859347022185518914214272644802222401413400694952754153652101 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
19547230 ps |
| T172 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.65643416318912618310359095735841338186243567193020076755603593738925666711011 |
|
|
Nov 22 01:20:34 PM PST 23 |
Nov 22 01:20:39 PM PST 23 |
19547230 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.23858426251058180779394930813434412184856677952699525264910230410862585625859 |
|
|
Nov 22 01:19:35 PM PST 23 |
Nov 22 01:19:44 PM PST 23 |
362187346 ps |
| T173 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.108106366045324679377376630169498307392023806530581927602515208833343821551411 |
|
|
Nov 22 01:20:04 PM PST 23 |
Nov 22 01:20:07 PM PST 23 |
117100021 ps |
| T174 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.22294918024732629444918098361867153935773056161130822463521931732998582518191 |
|
|
Nov 22 01:19:54 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
23886481 ps |
| T175 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.17648985734186358509472668800300882605273184405523035884879801081764024376778 |
|
|
Nov 22 01:19:49 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
23886481 ps |
| T176 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.77874049004641549340748128826576162104263097216942166022604341399284091122360 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:55 PM PST 23 |
23886481 ps |
| T177 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.68608819790509165515271702181415115516236423302636973523250428793907017275614 |
|
|
Nov 22 01:20:07 PM PST 23 |
Nov 22 01:20:09 PM PST 23 |
19547230 ps |
| T178 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.9358300372537806581393293375813618115561137567384768453991164881981374036858 |
|
|
Nov 22 01:19:38 PM PST 23 |
Nov 22 01:19:45 PM PST 23 |
23886481 ps |
| T179 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.49897033721943595653417566815730997249103618714608509491791052743466660781250 |
|
|
Nov 22 01:19:55 PM PST 23 |
Nov 22 01:20:00 PM PST 23 |
19547230 ps |
| T180 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.14703981804557102239583425229499104529573789725395596918334097324356243948692 |
|
|
Nov 22 01:19:54 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
42439904 ps |
| T181 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.13460307893174736278521491480544455202872249865895222189998915334498267957559 |
|
|
Nov 22 01:19:55 PM PST 23 |
Nov 22 01:20:00 PM PST 23 |
42439904 ps |
| T88 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.50868298478002042238990009199070756765420572877837268249586639266757208535063 |
|
|
Nov 22 01:19:53 PM PST 23 |
Nov 22 01:20:00 PM PST 23 |
362187346 ps |
| T182 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.35344207087126131876085535942104836476676219653903720130087161502267037731861 |
|
|
Nov 22 01:19:38 PM PST 23 |
Nov 22 01:19:45 PM PST 23 |
22582920 ps |
| T183 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.57083606263436282980166676028534201387376253986714166928351978894845757276708 |
|
|
Nov 22 01:19:46 PM PST 23 |
Nov 22 01:19:52 PM PST 23 |
122117838 ps |
| T184 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.13045751856660649503020527848423223453025413990491822605324368746543727589952 |
|
|
Nov 22 01:19:46 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
163313937 ps |
| T185 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.17048960809256976100334684237507470711898493728764594884669815066503580024518 |
|
|
Nov 22 01:20:33 PM PST 23 |
Nov 22 01:20:39 PM PST 23 |
42439904 ps |
| T186 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.28675151604462895937258019502856669953315675621985994696356394948549822384390 |
|
|
Nov 22 01:19:54 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
23886481 ps |
| T89 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.91097627221304618887338730079719624684597797198583968009709546570378284237156 |
|
|
Nov 22 01:20:03 PM PST 23 |
Nov 22 01:20:07 PM PST 23 |
362187346 ps |
| T187 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.7799886262796051734291511660442707757798024725687995963000403088678728394176 |
|
|
Nov 22 01:19:40 PM PST 23 |
Nov 22 01:19:48 PM PST 23 |
117100021 ps |
| T188 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.101630742544515552691595586033555755317039311660940184469289387613661462905793 |
|
|
Nov 22 01:19:52 PM PST 23 |
Nov 22 01:19:57 PM PST 23 |
42439904 ps |
| T189 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.55301225597065462426600121385056071557568874628244658385475871926404741238731 |
|
|
Nov 22 01:19:51 PM PST 23 |
Nov 22 01:19:58 PM PST 23 |
117100021 ps |
| T190 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.78450693560108860370145682862155610238955982728097626319459689198986703065705 |
|
|
Nov 22 01:19:49 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
23886481 ps |
| T191 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.63837900275081450224939668424984364748994281518907393524339178267918912259895 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:49 PM PST 23 |
23886481 ps |
| T192 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.91479072273175075306070035600393194863106187162924901989995271800029054899610 |
|
|
Nov 22 01:19:38 PM PST 23 |
Nov 22 01:19:46 PM PST 23 |
42439904 ps |
| T193 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.85942580501429618612513271456591972090175670803830137390028762629140392573014 |
|
|
Nov 22 01:20:04 PM PST 23 |
Nov 22 01:20:06 PM PST 23 |
23886481 ps |
| T90 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.99751429085359762324550072986149616624546979552585163912277138612780724798515 |
|
|
Nov 22 01:19:38 PM PST 23 |
Nov 22 01:19:47 PM PST 23 |
362187346 ps |
| T194 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.7699367062620728182965349957926331386081848309592874590431787377959916141965 |
|
|
Nov 22 01:20:04 PM PST 23 |
Nov 22 01:20:07 PM PST 23 |
163313937 ps |
| T195 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.58858551621889702820276308727602337265130006528830258127011400908844321094123 |
|
|
Nov 22 01:19:53 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
122117838 ps |
| T196 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.78586549581909820618534686109347446536629475475842355247167863385393907839789 |
|
|
Nov 22 01:19:51 PM PST 23 |
Nov 22 01:19:56 PM PST 23 |
19547230 ps |
| T197 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.31916764269661440356930809867431894549953244732369838650090498708899093002276 |
|
|
Nov 22 01:20:16 PM PST 23 |
Nov 22 01:20:19 PM PST 23 |
42439904 ps |
| T198 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.47302549845687521596771126527653938110672295168872168612144572873769122199420 |
|
|
Nov 22 01:19:46 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
117100021 ps |
| T199 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.7736057543356939407288076230138740212595468726907831534398721850139410061204 |
|
|
Nov 22 01:19:35 PM PST 23 |
Nov 22 01:19:42 PM PST 23 |
19547230 ps |
| T200 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.95640057402110074813327865964712316369342173334040905636566494252551596878894 |
|
|
Nov 22 01:19:39 PM PST 23 |
Nov 22 01:19:46 PM PST 23 |
23779339 ps |
| T201 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.4952281565772374971364403492063121619677453345316802155191118673957273890692 |
|
|
Nov 22 01:20:14 PM PST 23 |
Nov 22 01:20:18 PM PST 23 |
362187346 ps |
| T202 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.68004552515598517176285873730012749612904937691785856865985375250281683891349 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
19547230 ps |
| T203 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.111210369144860121794658045227355623083039400868727287079697250494112976732892 |
|
|
Nov 22 01:19:36 PM PST 23 |
Nov 22 01:19:43 PM PST 23 |
23886481 ps |
| T204 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.21640118229439219877363616122331570999554874256961973391992505770295316489899 |
|
|
Nov 22 01:19:43 PM PST 23 |
Nov 22 01:19:50 PM PST 23 |
42439904 ps |
| T205 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.33523699205170255826840903290509896875304609488642452149441176261702024192901 |
|
|
Nov 22 01:19:37 PM PST 23 |
Nov 22 01:19:44 PM PST 23 |
163313937 ps |
| T206 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.108287363851949525233282096048095334682194873719609682232769984482063781932991 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:55 PM PST 23 |
42439904 ps |
| T207 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.49256534505087259564197923704178608151190783820590900983820043443483782817306 |
|
|
Nov 22 01:20:05 PM PST 23 |
Nov 22 01:20:08 PM PST 23 |
163313937 ps |
| T208 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.100946209906833150035105828388771806891278535773644823935880487181859205223373 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:55 PM PST 23 |
163313937 ps |
| T209 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.63855570339184262154659509973109289362154607956795081038163077828500545018481 |
|
|
Nov 22 01:19:49 PM PST 23 |
Nov 22 01:19:56 PM PST 23 |
117100021 ps |
| T210 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.105327857447680993510959674168553836142711518776224635272306954909959884598002 |
|
|
Nov 22 01:19:36 PM PST 23 |
Nov 22 01:19:42 PM PST 23 |
42439904 ps |
| T211 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.70972529052789942649857724977370985461302969962050019404832726849628068485887 |
|
|
Nov 22 01:19:40 PM PST 23 |
Nov 22 01:19:46 PM PST 23 |
23886481 ps |
| T212 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.7190704105138391620292676973648826525904276986573908481804581040222611027995 |
|
|
Nov 22 01:19:38 PM PST 23 |
Nov 22 01:19:47 PM PST 23 |
117100021 ps |
| T213 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.24230074366302847188641141870498691440673437315977087525645900578284387501750 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:49 PM PST 23 |
42439904 ps |
| T214 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.82624350122360606170428538691719982108343155043264777863178543041131849273587 |
|
|
Nov 22 01:19:37 PM PST 23 |
Nov 22 01:19:46 PM PST 23 |
362187346 ps |
| T215 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4387352708546492315516285356288403907189969804313283653429668542695991288623 |
|
|
Nov 22 01:19:46 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
163313937 ps |
| T216 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.73695448191253724263137503358731545994436351972151025923872527451036011324383 |
|
|
Nov 22 01:19:49 PM PST 23 |
Nov 22 01:19:53 PM PST 23 |
23886481 ps |
| T217 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.97515405803305319841668511738335796956704522241451346420001341830053168766184 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:56 PM PST 23 |
362187346 ps |
| T218 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.72511336078264838835267305913811948868526514398123593360543743968238307266866 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:49 PM PST 23 |
22582920 ps |
| T219 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.90818558460245025625791724583292395222448303999906859556946807444997167917498 |
|
|
Nov 22 01:19:35 PM PST 23 |
Nov 22 01:19:41 PM PST 23 |
19547230 ps |
| T220 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.76641068878155866624610009332486907675865094359053871416737178231338383138552 |
|
|
Nov 22 01:20:25 PM PST 23 |
Nov 22 01:20:30 PM PST 23 |
23886481 ps |
| T221 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.51082621758534191823475596832053963699546187025240358594442787446239885574697 |
|
|
Nov 22 01:19:54 PM PST 23 |
Nov 22 01:20:01 PM PST 23 |
163313937 ps |
| T222 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.64160278501570190306527199776494444244281014462557859675940307942228258366982 |
|
|
Nov 22 01:19:52 PM PST 23 |
Nov 22 01:19:58 PM PST 23 |
163313937 ps |
| T223 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.18825599753572018064268589239735936383743529846490739158296365265137461760596 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:55 PM PST 23 |
117100021 ps |
| T224 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.612558875123317269398136336060669028747683589780663873965967708302732884735 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:56 PM PST 23 |
362187346 ps |
| T225 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.68183484612849079572279673268941195921520271529618783676271859369065941062298 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:55 PM PST 23 |
19547230 ps |
| T226 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.22937024108480776375185664722497461971361756697455679831022104077183056920281 |
|
|
Nov 22 01:19:49 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
23779339 ps |
| T227 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.50759051981567218529258820871050158729869386663658695554762341024464412478504 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
163313937 ps |
| T228 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.111280950271447359915840902270051363950117758937660693331248210120567825348776 |
|
|
Nov 22 01:20:04 PM PST 23 |
Nov 22 01:20:06 PM PST 23 |
19547230 ps |
| T229 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.20540568762557712705316764335195439831686808225924121824110457876173771387866 |
|
|
Nov 22 01:19:50 PM PST 23 |
Nov 22 01:19:55 PM PST 23 |
19547230 ps |
| T230 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.60648195364381642068265103469963512380757351676543998012437296067259743556540 |
|
|
Nov 22 01:19:49 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
42439904 ps |
| T231 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.24277553946059041994574079648469257146304958222502586918990466516895007726065 |
|
|
Nov 22 01:19:49 PM PST 23 |
Nov 22 01:19:54 PM PST 23 |
19547230 ps |
| T232 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.21836586940944478023012462791064583478390939789173665536173513262272315807434 |
|
|
Nov 22 01:19:39 PM PST 23 |
Nov 22 01:19:48 PM PST 23 |
362187346 ps |
| T233 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.47505195566816822580491020547172797199721610283604245364732007200592733386450 |
|
|
Nov 22 01:19:52 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
117100021 ps |
| T234 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.74900152034940443375455228517145841793743098805172123440607142961595195054735 |
|
|
Nov 22 01:20:34 PM PST 23 |
Nov 22 01:20:42 PM PST 23 |
362187346 ps |
| T235 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.13343786748517112141492097102901448899442007070416335946101062795258882982384 |
|
|
Nov 22 01:19:52 PM PST 23 |
Nov 22 01:19:58 PM PST 23 |
163313937 ps |
| T236 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.39179649918412738471865900625200888079209204192908336468170868406043619592045 |
|
|
Nov 22 01:20:51 PM PST 23 |
Nov 22 01:20:57 PM PST 23 |
163313937 ps |
| T237 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.58969973353480329515814286958066324674812560451051286682482706429255090289086 |
|
|
Nov 22 01:19:52 PM PST 23 |
Nov 22 01:20:00 PM PST 23 |
362187346 ps |
| T238 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.24370843579216515922702902163989431918213337622858669242229970258834085770601 |
|
|
Nov 22 01:20:04 PM PST 23 |
Nov 22 01:20:06 PM PST 23 |
163313937 ps |
| T239 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.70021960431785744599137763208341306972155498301520972683279592361618758649519 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:51 PM PST 23 |
362187346 ps |
| T240 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.76683178373923319445858241035133579666736679970919315042574679802308715297451 |
|
|
Nov 22 01:19:34 PM PST 23 |
Nov 22 01:19:38 PM PST 23 |
22582920 ps |
| T241 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.10462093361811655468994795252755977272324110622387823712884553035129469151170 |
|
|
Nov 22 01:19:32 PM PST 23 |
Nov 22 01:19:38 PM PST 23 |
117100021 ps |
| T242 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.69942723639798080629715708021615230350159237451298812709067389995574076926023 |
|
|
Nov 22 01:19:52 PM PST 23 |
Nov 22 01:19:59 PM PST 23 |
362187346 ps |
| T243 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.92873400841861889455525243785530824656581686666167109728287423579071578384636 |
|
|
Nov 22 01:19:48 PM PST 23 |
Nov 22 01:19:55 PM PST 23 |
117100021 ps |
| T244 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.38076547875381042446787350901237567823022004888219054591361580233736925058491 |
|
|
Nov 22 01:19:33 PM PST 23 |
Nov 22 01:19:37 PM PST 23 |
23886481 ps |
| T245 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.53633432324803528356072323311113587320942053632634015162192578828894113614914 |
|
|
Nov 22 01:19:36 PM PST 23 |
Nov 22 01:19:43 PM PST 23 |
19547230 ps |
| T246 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.103612007506538836847025077029823550436906469921374645314266683869062844606745 |
|
|
Nov 22 01:19:37 PM PST 23 |
Nov 22 01:19:45 PM PST 23 |
117100021 ps |
| T247 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.32922490899492211048740377386708372575801231695150379238736533621097615099682 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:51 PM PST 23 |
362187346 ps |
| T248 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.113032343931052855546912603758491979437863147778081512265700264847191668053654 |
|
|
Nov 22 01:19:41 PM PST 23 |
Nov 22 01:19:49 PM PST 23 |
19547230 ps |
| T249 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.23628624064854758990016792227812837816431860152939784685050966417037407052026 |
|
|
Nov 22 01:19:42 PM PST 23 |
Nov 22 01:19:48 PM PST 23 |
23779339 ps |
| T250 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.6632676054407902281624500598923414337871904708311143215904300810004289922875 |
|
|
Nov 22 01:20:34 PM PST 23 |
Nov 22 01:20:40 PM PST 23 |
42439904 ps |
| T251 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.24050586511191575009595924559966590137989167047775248875306916224932277518340 |
|
|
Nov 22 01:19:37 PM PST 23 |
Nov 22 01:19:45 PM PST 23 |
163313937 ps |
| T252 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.35766321607381949150757208891947718857800376017880257008384330730536773031083 |
|
|
Nov 22 01:21:17 PM PST 23 |
Nov 22 01:21:19 PM PST 23 |
40672061 ps |
| T253 |
/workspace/coverage/default/25.sram_ctrl_smoke.109132189863527251415557103711210727772827452708910733217039656236672004123004 |
|
|
Nov 22 01:22:02 PM PST 23 |
Nov 22 01:22:18 PM PST 23 |
427865392 ps |
| T254 |
/workspace/coverage/default/42.sram_ctrl_executable.50398041701435396650770539777471309067119776523862136864055449202420166144406 |
|
|
Nov 22 01:24:10 PM PST 23 |
Nov 22 01:34:24 PM PST 23 |
23162112088 ps |
| T255 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.57215075783307014582116403029038659230539527025605789680163735517394428935835 |
|
|
Nov 22 01:21:52 PM PST 23 |
Nov 22 01:22:03 PM PST 23 |
590810517 ps |
| T256 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.54752095701945943659449281108208200687001412903076724882519239103835493728839 |
|
|
Nov 22 01:23:04 PM PST 23 |
Nov 22 01:35:38 PM PST 23 |
21947461091 ps |
| T257 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.86444939092589841085728520730181556951282997669858202841261884994455733260507 |
|
|
Nov 22 01:22:03 PM PST 23 |
Nov 22 01:22:16 PM PST 23 |
985753786 ps |
| T258 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.104584699389604006111110735082679735704613482170965549899738246170700012476063 |
|
|
Nov 22 01:21:33 PM PST 23 |
Nov 22 01:21:52 PM PST 23 |
985753786 ps |
| T259 |
/workspace/coverage/default/8.sram_ctrl_executable.88866625934449268191083501009800986405917223816995442615443825648832850346578 |
|
|
Nov 22 01:21:48 PM PST 23 |
Nov 22 01:34:52 PM PST 23 |
23162112088 ps |
| T260 |
/workspace/coverage/default/0.sram_ctrl_partial_access.90648988034187229100865771627781314291149326127396628153838853330478484169605 |
|
|
Nov 22 01:21:26 PM PST 23 |
Nov 22 01:21:49 PM PST 23 |
445204539 ps |
| T261 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.61356899195948145609633024850401178326531010678475141442275039781796926236825 |
|
|
Nov 22 01:22:03 PM PST 23 |
Nov 22 01:22:09 PM PST 23 |
40672061 ps |