Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	58641200	1			T1	7231		T2	123171		T3	49152
triple_byte_access	3527550	1			T1	288		T2	2470		T4	5619
halfword_access	5303800	1			T1	475		T2	3737		T4	8360
byte_access	7041500	1			T1	633		T2	4701		T4	10958
zero_access	1775950	1			T1	162		T2	1222		T4	2767

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38078050

1

T1

4368

T2

67796

T3

24576

auto[1]

38211950

1

T1

4421

T2

67505

T3

24576

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	29276950	1			T1	3599		T2	61685		T3	24576
auto[0]	triple_byte_access	1754850	1			T1	148		T2	1246		T4	2798
auto[0]	halfword_access	2650950	1			T1	223		T2	1891		T4	4187
auto[0]	byte_access	3508300	1			T1	313		T2	2382		T4	5450
auto[0]	zero_access	887000	1			T1	85		T2	592		T4	1365
auto[1]	word_access	29364250	1			T1	3632		T2	61486		T3	24576
auto[1]	triple_byte_access	1772700	1			T1	140		T2	1224		T4	2821
auto[1]	halfword_access	2652850	1			T1	252		T2	1846		T4	4173
auto[1]	byte_access	3533200	1			T1	320		T2	2319		T4	5508
auto[1]	zero_access	888950	1			T1	77		T2	630		T4	1402