Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14955056	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

59070993

1

T1

6142

T2

5163

T3

68105

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36900687	1			T1	2048		T2	2579		T3	187194
values[0x0]	17066489	1			T1	2072		T2	1298		T3	62519
values[0x1]	20058873	1			T1	2022		T2	1286		T3	124228

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7453141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

66572908

1

T1

6142

T2

5163

T3

221744

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	285999	1			T1	32		T2	19		T3	1531
valid_sources[0x01]	333109	1			T1	20		T2	20		T3	1393
valid_sources[0x02]	253988	1			T1	24		T2	21		T3	1459
valid_sources[0x03]	388082	1			T1	26		T2	23		T3	1576
valid_sources[0x04]	270189	1			T1	25		T2	16		T3	1405
valid_sources[0x05]	349674	1			T1	25		T2	21		T3	1451
valid_sources[0x06]	298694	1			T1	30		T2	17		T3	1493
valid_sources[0x07]	319559	1			T1	23		T2	17		T3	1400
valid_sources[0x08]	311383	1			T1	19		T2	29		T3	1452
valid_sources[0x09]	262105	1			T1	27		T2	12		T3	1504
valid_sources[0x0a]	288677	1			T1	28		T2	21		T3	1439
valid_sources[0x0b]	300514	1			T1	26		T2	25		T3	1524
valid_sources[0x0c]	270999	1			T1	17		T2	23		T3	1502
valid_sources[0x0d]	292531	1			T1	26		T2	23		T3	1534
valid_sources[0x0e]	291150	1			T1	18		T2	16		T3	1547
valid_sources[0x0f]	266056	1			T1	24		T2	19		T3	1408
valid_sources[0x10]	256026	1			T1	21		T2	15		T3	1329
valid_sources[0x11]	256464	1			T1	16		T2	24		T3	1392
valid_sources[0x12]	291019	1			T1	25		T2	26		T3	1343
valid_sources[0x13]	278424	1			T1	15		T2	13		T3	1515
valid_sources[0x14]	306064	1			T1	28		T2	26		T3	1431
valid_sources[0x15]	254764	1			T1	17		T2	13		T3	1479
valid_sources[0x16]	268458	1			T1	25		T2	16		T3	1400
valid_sources[0x17]	289270	1			T1	23		T2	24		T3	1408
valid_sources[0x18]	374747	1			T1	22		T2	19		T3	1453
valid_sources[0x19]	280897	1			T1	32		T2	19		T3	1493
valid_sources[0x1a]	262137	1			T1	30		T2	18		T3	1324
valid_sources[0x1b]	263382	1			T1	37		T2	21		T3	1518
valid_sources[0x1c]	271999	1			T1	24		T2	19		T3	1392
valid_sources[0x1d]	339445	1			T1	21		T2	26		T3	1524
valid_sources[0x1e]	255667	1			T1	23		T2	16		T3	1499
valid_sources[0x1f]	265502	1			T1	13		T2	24		T3	1546
valid_sources[0x20]	300383	1			T1	24		T2	25		T3	1549
valid_sources[0x21]	265698	1			T1	22		T2	18		T3	1447
valid_sources[0x22]	268074	1			T1	22		T2	18		T3	1626
valid_sources[0x23]	268999	1			T1	24		T2	24		T3	1441
valid_sources[0x24]	256080	1			T1	26		T2	16		T3	1570
valid_sources[0x25]	255785	1			T1	20		T2	21		T3	1422
valid_sources[0x26]	272702	1			T1	24		T2	22		T3	1447
valid_sources[0x27]	271257	1			T1	31		T2	15		T3	1385
valid_sources[0x28]	287042	1			T1	22		T2	35		T3	1438
valid_sources[0x29]	275307	1			T1	26		T2	23		T3	1371
valid_sources[0x2a]	250010	1			T1	19		T2	24		T3	1549
valid_sources[0x2b]	287007	1			T1	26		T2	29		T3	1588
valid_sources[0x2c]	259958	1			T1	27		T2	20		T3	1415
valid_sources[0x2d]	288563	1			T1	20		T2	19		T3	1350
valid_sources[0x2e]	268772	1			T1	20		T2	26		T3	1514
valid_sources[0x2f]	248596	1			T1	18		T2	17		T3	1336
valid_sources[0x30]	253909	1			T1	24		T2	21		T3	1434
valid_sources[0x31]	345511	1			T1	27		T2	14		T3	1551
valid_sources[0x32]	316947	1			T1	24		T2	20		T3	1435
valid_sources[0x33]	291911	1			T1	23		T2	17		T3	1462
valid_sources[0x34]	254149	1			T1	21		T2	17		T3	1428
valid_sources[0x35]	251312	1			T1	25		T2	15		T3	1531
valid_sources[0x36]	262829	1			T1	22		T2	24		T3	1494
valid_sources[0x37]	266148	1			T1	26		T2	22		T3	1302
valid_sources[0x38]	379056	1			T1	18		T2	18		T3	1429
valid_sources[0x39]	247561	1			T1	31		T2	22		T3	1368
valid_sources[0x3a]	287669	1			T1	23		T2	19		T3	1526
valid_sources[0x3b]	272807	1			T1	25		T2	25		T3	1434
valid_sources[0x3c]	272723	1			T1	23		T2	21		T3	1449
valid_sources[0x3d]	258922	1			T1	22		T2	21		T3	1347
valid_sources[0x3e]	294056	1			T1	16		T2	21		T3	1458
valid_sources[0x3f]	262346	1			T1	34		T2	21		T3	1485
valid_sources[0x40]	283479	1			T1	32		T2	15		T3	1499
valid_sources[0x41]	299968	1			T1	19		T2	17		T3	1576
valid_sources[0x42]	271350	1			T1	19		T2	16		T3	1439
valid_sources[0x43]	314272	1			T1	40		T2	21		T3	1339
valid_sources[0x44]	284518	1			T1	22		T2	23		T3	1483
valid_sources[0x45]	294072	1			T1	17		T2	22		T3	1433
valid_sources[0x46]	302235	1			T1	23		T2	19		T3	1419
valid_sources[0x47]	325322	1			T1	17		T2	18		T3	1626
valid_sources[0x48]	308547	1			T1	24		T2	18		T3	1370
valid_sources[0x49]	295037	1			T1	20		T2	17		T3	1329
valid_sources[0x4a]	252450	1			T1	19		T2	15		T3	1705
valid_sources[0x4b]	252511	1			T1	19		T2	15		T3	1436
valid_sources[0x4c]	331683	1			T1	31		T2	20		T3	1462
valid_sources[0x4d]	289481	1			T1	29		T2	19		T3	1530
valid_sources[0x4e]	286449	1			T1	20		T2	18		T3	1424
valid_sources[0x4f]	267814	1			T1	20		T2	16		T3	1378
valid_sources[0x50]	297273	1			T1	22		T2	15		T3	1442
valid_sources[0x51]	259372	1			T1	37		T2	21		T3	1523
valid_sources[0x52]	272082	1			T1	24		T2	22		T3	1478
valid_sources[0x53]	408242	1			T1	23		T2	20		T3	1355
valid_sources[0x54]	249422	1			T1	22		T2	14		T3	1488
valid_sources[0x55]	250750	1			T1	29		T2	21		T3	1384
valid_sources[0x56]	300885	1			T1	22		T2	22		T3	1404
valid_sources[0x57]	333501	1			T1	17		T2	19		T3	1441
valid_sources[0x58]	267467	1			T1	26		T2	20		T3	1325
valid_sources[0x59]	311445	1			T1	19		T2	15		T3	1463
valid_sources[0x5a]	309224	1			T1	25		T2	29		T3	1423
valid_sources[0x5b]	275776	1			T1	28		T2	19		T3	1487
valid_sources[0x5c]	311513	1			T1	22		T2	21		T3	1609
valid_sources[0x5d]	248053	1			T1	30		T2	13		T3	1412
valid_sources[0x5e]	252779	1			T1	21		T2	15		T3	1368
valid_sources[0x5f]	309806	1			T1	15		T2	16		T3	1327
valid_sources[0x60]	302172	1			T1	24		T2	25		T3	1493
valid_sources[0x61]	252593	1			T1	19		T2	18		T3	1391
valid_sources[0x62]	281430	1			T1	23		T2	29		T3	1533
valid_sources[0x63]	316354	1			T1	22		T2	27		T3	1350
valid_sources[0x64]	270833	1			T1	23		T2	23		T3	1506
valid_sources[0x65]	268232	1			T1	20		T2	12		T3	1450
valid_sources[0x66]	285972	1			T1	19		T2	17		T3	1389
valid_sources[0x67]	340259	1			T1	25		T2	18		T3	1503
valid_sources[0x68]	261949	1			T1	38		T2	14		T3	1423
valid_sources[0x69]	275290	1			T1	18		T2	17		T3	1349
valid_sources[0x6a]	279361	1			T1	25		T2	20		T3	1526
valid_sources[0x6b]	268260	1			T1	20		T2	21		T3	1527
valid_sources[0x6c]	401771	1			T1	20		T2	17		T3	1378
valid_sources[0x6d]	256902	1			T1	26		T2	21		T3	1512
valid_sources[0x6e]	288494	1			T1	24		T2	11		T3	1450
valid_sources[0x6f]	307780	1			T1	23		T2	27		T3	1557
valid_sources[0x70]	291685	1			T1	34		T2	20		T3	1414
valid_sources[0x71]	256697	1			T1	22		T2	23		T3	1391
valid_sources[0x72]	256235	1			T1	25		T2	16		T3	1362
valid_sources[0x73]	286955	1			T1	16		T2	14		T3	1497
valid_sources[0x74]	254868	1			T1	24		T2	16		T3	1511
valid_sources[0x75]	332516	1			T1	23		T2	23		T3	1462
valid_sources[0x76]	268438	1			T1	19		T2	29		T3	1498
valid_sources[0x77]	260893	1			T1	24		T2	22		T3	1484
valid_sources[0x78]	290371	1			T1	20		T2	23		T3	1436
valid_sources[0x79]	293413	1			T1	26		T2	16		T3	1531
valid_sources[0x7a]	275480	1			T1	31		T2	28		T3	1449
valid_sources[0x7b]	263618	1			T1	23		T2	14		T3	1454
valid_sources[0x7c]	285226	1			T1	20		T2	12		T3	1566
valid_sources[0x7d]	298291	1			T1	30		T2	31		T3	1433
valid_sources[0x7e]	269856	1			T1	28		T2	24		T3	1465
valid_sources[0x7f]	309721	1			T1	29		T2	19		T3	1504
valid_sources[0x80]	357121	1			T1	30		T2	20		T3	1431

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29429261

1

T1

2048

T2

2579

T3

34223

values[0x0]

all_enables

biggest_size

14822073

1

T1

2072

T2

1298

T3

16878

values[0x1]

all_enables

biggest_size

14819659

1

T1

2022

T2

1286

T3

17004

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2331214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

133872

1

T2

2

T3

4

T4

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2348109	1			T2	1066		T3	1053		T4	1587
values[0x0]	57077	1			T2	2		T3	4		T4	3
values[0x1]	59900	1			T3	3		T4	4		T9	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1557984	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

907102

1

T2

347

T3

353

T4

518

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8983	1			T3	2		T4	1		T5	48
valid_sources[0x01]	9043	1			T3	5		T4	3		T5	27
valid_sources[0x02]	9416	1			T3	1		T4	11		T5	35
valid_sources[0x03]	8989	1			T2	2		T3	7		T4	23
valid_sources[0x04]	7887	1			T3	5		T5	46		T6	8
valid_sources[0x05]	8998	1			T2	1		T3	3		T4	1
valid_sources[0x06]	7192	1			T2	18		T3	5		T4	3
valid_sources[0x07]	10521	1			T3	6		T4	1		T5	37
valid_sources[0x08]	8056	1			T2	7		T3	2		T4	9
valid_sources[0x09]	7162	1			T2	13		T3	2		T4	22
valid_sources[0x0a]	11369	1			T3	3		T4	2		T5	23
valid_sources[0x0b]	19705	1			T2	3		T3	5		T4	9
valid_sources[0x0c]	7060	1			T3	3		T4	5		T5	25
valid_sources[0x0d]	8060	1			T3	2		T4	6		T5	26
valid_sources[0x0e]	8092	1			T2	9		T3	4		T4	8
valid_sources[0x0f]	7360	1			T3	3		T4	3		T5	35
valid_sources[0x10]	7197	1			T3	1		T4	5		T5	50
valid_sources[0x11]	7944	1			T2	5		T3	6		T4	3
valid_sources[0x12]	9887	1			T2	6		T3	2		T4	6
valid_sources[0x13]	9473	1			T3	4		T4	10		T5	32
valid_sources[0x14]	7420	1			T2	2		T3	8		T4	22
valid_sources[0x15]	7402	1			T3	6		T4	4		T5	41
valid_sources[0x16]	7177	1			T3	6		T4	2		T5	24
valid_sources[0x17]	7607	1			T3	4		T4	5		T5	41
valid_sources[0x18]	7747	1			T2	6		T3	8		T4	1
valid_sources[0x19]	10033	1			T2	10		T3	2		T4	9
valid_sources[0x1a]	11782	1			T3	6		T4	7		T5	33
valid_sources[0x1b]	7442	1			T3	3		T4	2		T10	1
valid_sources[0x1c]	9372	1			T2	10		T3	5		T4	2
valid_sources[0x1d]	13556	1			T2	2		T4	2		T5	26
valid_sources[0x1e]	7885	1			T3	4		T4	9		T5	39
valid_sources[0x1f]	7590	1			T2	3		T3	1		T5	32
valid_sources[0x20]	7173	1			T3	4		T4	4		T5	29
valid_sources[0x21]	7275	1			T3	3		T4	3		T5	27
valid_sources[0x22]	7355	1			T2	14		T3	7		T4	11
valid_sources[0x23]	16284	1			T2	6		T3	9		T4	11
valid_sources[0x24]	7201	1			T3	5		T4	12		T5	28
valid_sources[0x25]	7313	1			T3	2		T4	4		T5	30
valid_sources[0x26]	10495	1			T2	6		T3	2		T4	15
valid_sources[0x27]	7420	1			T2	8		T3	2		T4	4
valid_sources[0x28]	8117	1			T2	5		T3	7		T4	19
valid_sources[0x29]	8919	1			T3	7		T4	3		T5	33
valid_sources[0x2a]	21167	1			T2	2		T3	4		T4	8
valid_sources[0x2b]	9312	1			T3	6		T4	5		T5	30
valid_sources[0x2c]	7932	1			T3	3		T4	9		T5	34
valid_sources[0x2d]	7209	1			T2	2		T3	3		T4	7
valid_sources[0x2e]	9947	1			T3	3		T4	4		T5	34
valid_sources[0x2f]	6980	1			T2	7		T4	4		T5	25
valid_sources[0x30]	14512	1			T2	6		T3	4		T4	13
valid_sources[0x31]	7622	1			T3	5		T5	34		T6	2
valid_sources[0x32]	8372	1			T2	1		T3	5		T5	36
valid_sources[0x33]	7690	1			T3	7		T4	17		T5	28
valid_sources[0x34]	8333	1			T3	1		T4	14		T5	28
valid_sources[0x35]	7726	1			T3	1		T4	4		T11	5
valid_sources[0x36]	7476	1			T2	4		T3	7		T4	1
valid_sources[0x37]	7625	1			T3	2		T4	3		T5	32
valid_sources[0x38]	7647	1			T2	1		T3	3		T4	10
valid_sources[0x39]	7200	1			T3	2		T4	4		T5	38
valid_sources[0x3a]	7245	1			T3	3		T5	33		T6	14
valid_sources[0x3b]	12563	1			T2	15		T3	3		T5	42
valid_sources[0x3c]	10576	1			T2	6		T3	4		T4	7
valid_sources[0x3d]	8084	1			T2	1		T3	3		T4	6
valid_sources[0x3e]	7745	1			T3	2		T4	10		T5	32
valid_sources[0x3f]	7923	1			T2	34		T3	2		T5	36
valid_sources[0x40]	8895	1			T2	11		T3	3		T4	15
valid_sources[0x41]	8254	1			T2	2		T3	5		T4	11
valid_sources[0x42]	12569	1			T2	3		T3	1		T4	3
valid_sources[0x43]	10597	1			T2	7		T3	6		T4	20
valid_sources[0x44]	8042	1			T2	3		T3	4		T4	3
valid_sources[0x45]	8736	1			T2	23		T3	6		T4	5
valid_sources[0x46]	7403	1			T4	8		T5	37		T6	6
valid_sources[0x47]	7264	1			T3	3		T4	6		T5	32
valid_sources[0x48]	9478	1			T2	3		T3	4		T5	34
valid_sources[0x49]	7243	1			T3	5		T4	3		T5	42
valid_sources[0x4a]	7422	1			T3	3		T4	4		T5	26
valid_sources[0x4b]	7524	1			T3	8		T4	12		T5	36
valid_sources[0x4c]	7354	1			T3	2		T4	10		T5	45
valid_sources[0x4d]	9720	1			T2	15		T3	1		T4	3
valid_sources[0x4e]	14229	1			T2	8		T3	7		T4	1
valid_sources[0x4f]	7326	1			T3	4		T4	7		T5	35
valid_sources[0x50]	10292	1			T3	6		T4	8		T5	27
valid_sources[0x51]	7367	1			T3	1		T4	5		T5	34
valid_sources[0x52]	7387	1			T3	9		T4	3		T5	39
valid_sources[0x53]	9055	1			T2	16		T3	5		T4	1
valid_sources[0x54]	16858	1			T3	5		T4	13		T5	37
valid_sources[0x55]	7504	1			T2	7		T3	6		T4	1
valid_sources[0x56]	10431	1			T2	2		T3	2		T4	8
valid_sources[0x57]	11564	1			T3	1		T4	6		T5	38
valid_sources[0x58]	8132	1			T2	2		T3	1		T5	42
valid_sources[0x59]	7188	1			T2	7		T3	6		T4	5
valid_sources[0x5a]	7744	1			T3	5		T4	4		T5	36
valid_sources[0x5b]	14861	1			T3	3		T4	4		T5	34
valid_sources[0x5c]	8091	1			T2	6		T3	1		T4	5
valid_sources[0x5d]	34248	1			T2	2		T3	3		T4	14
valid_sources[0x5e]	10462	1			T2	16		T3	2		T4	18
valid_sources[0x5f]	7508	1			T3	5		T4	3		T5	31
valid_sources[0x60]	9013	1			T2	7		T3	6		T4	6
valid_sources[0x61]	6696	1			T2	2		T3	3		T4	2
valid_sources[0x62]	7695	1			T2	2		T3	8		T4	7
valid_sources[0x63]	7565	1			T3	4		T5	40		T6	8
valid_sources[0x64]	8074	1			T3	3		T4	11		T5	35
valid_sources[0x65]	8470	1			T2	1		T3	3		T4	9
valid_sources[0x66]	11126	1			T2	15		T3	11		T4	29
valid_sources[0x67]	7372	1			T3	7		T4	10		T5	26
valid_sources[0x68]	7533	1			T2	2		T3	8		T4	4
valid_sources[0x69]	7413	1			T3	2		T4	11		T5	35
valid_sources[0x6a]	7675	1			T2	7		T3	2		T4	5
valid_sources[0x6b]	8600	1			T2	14		T3	9		T5	42
valid_sources[0x6c]	23068	1			T3	2		T5	32		T6	5
valid_sources[0x6d]	7649	1			T3	4		T4	2		T5	28
valid_sources[0x6e]	7252	1			T3	4		T4	2		T5	29
valid_sources[0x6f]	7024	1			T3	8		T4	8		T5	27
valid_sources[0x70]	8895	1			T2	2		T3	5		T5	35
valid_sources[0x71]	7646	1			T3	1		T4	2		T5	35
valid_sources[0x72]	7755	1			T3	7		T4	11		T5	24
valid_sources[0x73]	9878	1			T3	5		T4	9		T5	21
valid_sources[0x74]	14847	1			T3	5		T4	1		T5	27
valid_sources[0x75]	11116	1			T3	5		T4	2		T5	30
valid_sources[0x76]	7784	1			T4	8		T5	29		T12	1
valid_sources[0x77]	7879	1			T3	9		T4	4		T5	44
valid_sources[0x78]	8644	1			T2	2		T3	1		T4	3
valid_sources[0x79]	7896	1			T3	3		T4	7		T5	40
valid_sources[0x7a]	7518	1			T2	7		T3	4		T4	13
valid_sources[0x7b]	8433	1			T2	12		T3	3		T4	1
valid_sources[0x7c]	11083	1			T2	4		T3	2		T4	2
valid_sources[0x7d]	7360	1			T2	24		T3	7		T4	11
valid_sources[0x7e]	7244	1			T2	4		T3	3		T4	17
valid_sources[0x7f]	18082	1			T2	5		T3	3		T5	30
valid_sources[0x80]	7398	1			T3	5		T4	10		T5	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36491

1

T5

18

T7

34

T8

16

values[0x0]

all_enables

biggest_size

49666

1

T2

2

T3

4

T4

2

values[0x1]

all_enables

biggest_size

47715

1

T4

1

T9

1

T5

2