Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14636715

1

T3

305836

T4

3184

T5

119

full_word

53992960

1

T1

6142

T2

5163

T3

68105

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	68629355	1			T1	6142		T2	5163		T3	373941
auto[TlIntgErrCmd]	116	1			T42	3		T43	10		T51	7
auto[TlIntgErrData]	104	1			T42	3		T43	5		T51	11
auto[TlIntgErrBoth]	100	1			T42	4		T43	5		T51	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31425945

1

T1

2048

T2

2579

T3

187194

auto[1]

37203730

1

T1

4094

T2

2584

T3

186747

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7008349	1			T3	152971		T4	1606		T5	63
auto[TlIntgErrNone]	partial	auto[1]	7628068	1			T3	152865		T4	1578		T5	56
auto[TlIntgErrNone]	full_word	auto[0]	24417465	1			T1	2048		T2	2579		T3	34223
auto[TlIntgErrNone]	full_word	auto[1]	29575473	1			T1	4094		T2	2584		T3	33882
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T43	4		T51	3		T91	1
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T42	2		T43	5		T51	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T42	1		T118	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T43	1		T109	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T42	2		T43	1		T51	3
auto[TlIntgErrData]	partial	auto[1]	50	1			T43	4		T51	8		T91	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T42	1		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T115	1		T112	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T42	2		T91	2		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T42	2		T43	4		T51	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T43	1		T51	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T113	1		T115	1		T116	1